Methods of forming epitaxial semiconductor material in trenches located above the source and drain regions of a semiconductor device

Patent metadata

Field	Value
Publication number	US-9312388-B2
Application number	US-201414267216-A
Country	US
Kind code	B2
Filing date	May 1, 2014
Priority date	May 1, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, wherein a first portion of the gate structure is positioned above the active region and second portions of the gate structure are positioned above an isolation region formed in the substrate, forming a sidewall spacer adjacent opposite sides of the first portion of the gate structure so as to define first and second continuous epi formation trenches comprised of the spacer that extend for less than the axial length of the gate structure, and forming an epi semiconductor material on the active region within each of the first and second continuous epi formation trenches.

First claim

What is claimed:

1. A method of forming a device comprised of a gate structure, a source region and a drain region that are positioned on opposite sides of said gate structure, wherein the method comprises:
forming said gate structure above an active region of a semiconductor substrate, said gate structure having an axial length in a gate width direction of said device, wherein a first portion of said gate structure is positioned above said active region and second portions of said gate structure are positioned above an isolation region formed in said substrate;
forming an etch stop layer on said gate structure, wherein said etch stop layer covers end surfaces and sidewall surfaces of said second portions of said gate structure but does not cover any sidewall surfaces of said first portion of said gate structure;
forming a sidewall spacer adjacent opposite sides of said first portion of said gate structure so as to define first and second epi formation trenches comprising said spacer and extending continuously along said first portion of said gate structure for less than said axial length of said gate structure, wherein said first epi formation trench is positioned above at least a portion of said source region and said second epi formation trench is positioned above at least a portion of said drain region; and
forming an epi semiconductor material on said active region within each of said first and second epi formation trenches.

2. The method of claim 1 , wherein said first and second epi formation trenches are positioned adjacent said first portion of said gate structure but not adjacent said second portions of said gate structure.

3. The method of claim 1 , wherein said device is one of a planar device or a FinFET device.

4. The method of claim 1 , wherein said gate structure is one of a sacrificial gate structure or a final gate structure for said device.

5. The method of claim 1 , wherein said first and second epi formation trenches have a height that is approximately equal to a combined height of said gate structure and a gate cap layer formed above said gate structure.

6. The method of claim 1 , wherein said first and second epi formation trenches are in contact with first and second opposing sidewalls, respectively, of said gate structure.

7. The method of claim 1 , wherein forming said sidewall spacer defining said first epi formation trench comprises forming a first portion of a first sidewall spacer adjacent a first sidewall on a source region side of said gate structure and forming a second portion of said first spacer adjacent a sidewall of a first dummy gate structure positioned laterally adjacent and spaced apart from said first sidewall on said source region side of said gate structure.

8. The method of claim 7 , wherein forming said sidewall spacer defining said second epi formation trench comprises forming a first portion of a second sidewall spacer adjacent a second sidewall on a drain region side of said gate structure and forming a second portion of said second spacer adjacent a sidewall of a second dummy gate structure positioned laterally adjacent and spaced apart from said first sidewall on said drain region side of said gate structure.

9. The method of claim 1 , wherein forming said sidewall spacer defining said first epi formation trench comprises forming a first portion of a first sidewall spacer adjacent a first sidewall on a source region side of said gate structure and forming a second portion of said first spacer adjacent a sidewall of a layer of insulating material that is laterally adjacent and spaced apart from said first sidewall on said source region side of said gate structure.

10. The method of claim 9 , wherein forming said sidewall spacer defining said second epi formation trench comprises forming a first portion of a second sidewall spacer adjacent a second sidewall on a drain region side of said gate structure and forming a second portion of said second spacer adjacent a sidewall of a layer of insulating material that is laterally adjacent and spaced apart from said first sidewall on said drain region side of said gate structure.

11. The method of claim 1 , wherein forming said etch stop layer comprises:
forming a conformal layer of etch stop material that covers sidewall surfaces of said first portion of said gate structure and covers said end surfaces and said sidewall surfaces of said second portions of said gate structure; and
performing one or more etching processes to remove said conformal layer of etch stop material from said sidewalls of said first portion of said gate structure.

12. A method of forming a device comprised of a gate structure, a source region and a drain region that are positioned on opposite sides of said gate structure, wherein the method comprises:
forming said gate structure above an active region of a semiconductor substrate, said gate structure having sidewalls and opposing end surfaces, wherein a first portion of said gate structure is positioned above said active region and second portions of said gate structure are positioned above an isolation region formed in said substrate;
forming an etch stop layer on said sidewalls and said end surfaces of an entirety of said gate structure;
removing the portions of said etch stop layer positioned on said first portion of said gate structure while leaving said etch stop layer positioned on said second portions of said gate structure;
forming a sidewall spacer adjacent opposite sides of said first portion of said gate structure so as to define first and second epi formation trenches comprising said spacer and extending continuously along said first portion of said gate structure, wherein said first epi formation trench is positioned above at least a portion of said source region and said second epi formation trench is positioned above at least a portion of said drain region; and
forming an epi semiconductor material on said active region within each of said first and second epi formation trenches.

13. The method of claim 12 , wherein said etch stop layer is comprised of a material having a dielectric constant equal to or greater than 9.

14. The method of claim 12 , wherein said gate structure is a sacrificial gate structure and wherein the method further comprises:
after forming said epi semiconductor material, removing said sacrificial gate structure so as to define a gate cavity;
forming a gate insulation layer in said gate cavity and on said first and second epi formation trenches and on said first etch stop layer;
forming conductive material in said gate cavity on said gate insulation layer;
recessing said gate insulation layer and said conductive material within said gate cavity; and
forming a gate cap layer within said gate cavity above said recessed gate insulation layer and above said recessed conductive material.

15. The method of claim 12 , wherein said first and second epi formation trenches have a height that is approximately equal to a combined height of said gate structure and a gate cap layer formed above said gate structure.

16. The method of claim 12 , wherein said first and second epi formation trenches are in contact with first and second opposing sidewalls, respectively, of said gate structure.

17. The method of claim 12 , wherein forming said sidewall spacer defining said first epi formation trench comprises forming a first portion of a first sidewall spacer adjacent a first sidewall on a source region side of said gate structure and forming a second portion of said first spacer adjacent a sidewall of a first dummy gate structure position

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Kim Hoon
• Park Chanro
• Sung Min Gyu

Classifications

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title