Substrate design for semiconductor packages and method of forming same

Patent metadata

Field	Value
Publication number	US-10056267-B2
Application number	US-201414181305-A
Country	US
Kind code	B2
Filing date	Feb 14, 2014
Priority date	Feb 14, 2014
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

An embodiment device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

First claim

What is claimed is:

1. A device comprising:
a first die;
one or more redistribution layers (RDLs) electrically connected to the first die;
a first plurality of connectors on a surface of the one or more RDLs, the one or more RDLs being interposed between the first plurality of connectors and the first die;
a second die;
a package substrate electrically connected to the first die and the second die, wherein the package substrate comprises:
a metal-clad insulated base material core, the metal-clad insulated base material core having an upper-most surface and a lower-most surface, wherein the lower-most surface is closer to the one or more RDLs than the upper-most surface; and
a cavity extending through the metal-clad insulated base material core, wherein the second die is at least partially disposed in the cavity, and wherein the first die is electrically connected to the package substrate through the first plurality of connectors and the one or more RDLs; and

a second plurality of connectors in the cavity, the second plurality of connectors bonding the second die to the package substrate, the second plurality of connectors extending toward a bottommost surface of the cavity below the upper-most surface of the metal-clad insulated base material core, the second plurality of connectors directly contacting the package substrate along the bottommost surface of the cavity.

2. The device of claim 1 , wherein the first die and the second die are disposed on opposing sides of the package substrate.

3. The device of claim 2 , further comprising a first heat dissipation feature on a surface of the second die.

4. The device of claim 3 , wherein the package substrate comprises one or more interconnect structures electrically connecting the first die to the second die.

5. The device of claim 1 , further comprising a second heat dissipation feature on a surface of the first die.

6. The device of claim 1 , wherein the cavity does not extend completely through the package substrate.

7. The device of claim 1 , wherein the package substrate further comprises:
first build-up layers, wherein the cavity extends through the first build-up layers; and
second build-up layers on an opposing side of the metal-clad insulated base material core as the first build-up layers, wherein the cavity exposes the second build-up layers.

8. The device of claim 1 , further comprising a molding compound encapsulating the first die, the molding compound extending along a sidewall of the first die.

9. A device comprising:
a first die;
one or more redistribution layers (RDLs) on the first die;
a first plurality of connectors on a surface of the one or more RDLs, the one or more RDLs being interposed between the first plurality of connectors and the first die;
a second die;
a package substrate electrically connected to the first die and the second die, wherein the package substrate is electrically connected to the first die through the one or more RDLs and the first plurality of connectors, and wherein the package substrate comprises:
a core;
one or more first build-up layers on a first side of the core; and
one or more second build-up layers on a second side of the core opposite the first side, wherein the one or more second build-up layers and the core are patterned to form a cavity in the package substrate, wherein the second die is at least partially disposed in the cavity, wherein the cavity exposes a surface of the one or more first build-up layers substantially level with a surface of the core, and wherein an upper-most surface and a lower-most surface of material forming the core are interposed between the one or more first build-up layers and the one or more second build-up layers; and

a second plurality of connectors in the cavity, the second die being bonded to the package substrate through the second plurality of connectors, portions of the second plurality of connectors extending between an upper-most surface of the core and a lower-most surface of the core, the upper-most surface of the core being opposite the lower-most surface of the core, the lower-most surface of the core facing the one or more RDLs.

10. The device of claim 9 , wherein the cavity is disposed on an opposing side of the package substrate as the first die.

11. The device of claim 9 , wherein at least one of the one or more first build-up layers is disposed between the first die and the second die.

12. The device of claim 9 , wherein the core comprises a metal-clad insulated base material.

13. The device of claim 9 , further comprising a heat dissipation feature on a surface of the second die.

14. The device of claim 9 , further comprising a heat dissipation feature on a surface of the first die.

15. The device of claim 14 , further comprising a molding compound encapsulating the first die, at least a portion of the molding compound being interposed between the heat dissipation feature and the one or more RDLs.

16. A method comprising:
forming one or more redistribution layers (RDLs) on a first side of a first die;
forming first connectors on the one or more RDLs, the one or more RDLs being interposed between the first connectors and the first die;
forming a cavity extending at least partially through a package substrate, wherein the package substrate comprises:
one or more first build-up layers on a first side of a metal-clad insulated base material core; and
one or more second build-up layers on an opposing second side of the metal-clad insulated base material core, wherein forming the cavity comprises patterning the cavity through the one or more first build-up layers and the metal-clad insulated base material core to expose a surface of the one or more second build-up layers, and wherein a top surface and a bottom surface of material forming the metal-clad insulated base material core are interposed between the one or more first build-up layers and the one or more second build-up layers;

bonding the package substrate to the first die using the first connectors, wherein the package substrate is electrically connected to the first die through the one or more RDLs; and
electrically connecting a second die to the package substrate, wherein the second die is at least partially disposed in the cavity, wherein electrically connecting the second die comprises forming second connectors on the second die and bonding the second die to a surface of the package substrate in the cavity using the second connectors, and wherein a sidewall of at least one of the second connectors faces a sidewall of a portion of the cavity disposed within the metal-clad insulated base material core.

17. The method of claim 16 further comprising attaching a heat dissipation feature to a surface of the first die.

18. The method of claim 17 further comprising attaching a heat dissipation feature to a surface of the second die.

19. The method of claim 16 , further comprising forming a molding compound along a sidewall of the first die.

20. The method of claim 19 , wherein one or more RDLs extend along an upper-most surface of the molding compound.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Jung Wei
• Wang Tsung-Ding
• Lii Mirng-Ji
• Lee Chien-Hsun
• Yu Chen-Hua

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title