Integrated circuit package and methods of forming same

Patent metadata

Field	Value
Publication number	US-9653442-B2
Application number	US-201414252232-A
Country	US
Kind code	B2
Filing date	Apr 14, 2014
Priority date	Jan 17, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.

First claim

What is claimed is:

1. A package-on-package (PoP) device comprising:
a first package structure comprising:
a logic chip bonded to a memory chip by a first plurality of connectors, active surfaces of the logic chip and the memory chip facing each other;
a first molding compound encircling the memory chip; and
a first plurality of conductive studs laterally adjacent the memory chip and the first plurality of connectors, the first plurality of conductive studs contacting contact pads on the logic chip, the first plurality of conductive studs extending through the first molding compound from a first plane to the contact pads of the logic chip, the first plane being level with a backside surface of the memory chip, wherein an entirety of the first plurality of conductive studs are disposed in the first molding compound;

a first package substrate; and
a second plurality of connectors bonding the first package structure to the first package substrate.

2. The PoP device of claim 1 , further comprising one or more redistribution layers (RDLs) on a surface of the memory chip opposite the logic chip, wherein the second plurality of connectors are disposed on a surface of the one or more RDLs opposite the memory chip.

3. The PoP device of claim 2 , wherein the first plurality of conductive studs electrically connects the logic chip to the one or more RDLs.

4. The PoP device of claim 2 , wherein the one or more RDLs extends past edges of the memory chip onto the first molding compound and the first plurality of conductive studs.

5. The PoP device of claim 1 , further comprising:
a second molding compound encircling the first package structure; and
a second plurality of conductive studs adjacent the logic chip and the memory chip, wherein the second plurality of conductive studs extends through the second molding compound and is attached to contact pads on the first package substrate.

6. The PoP device of claim 5 , further comprising:
a second package structure; and
a third plurality of connectors electrically connecting the second package structure to the first package substrate, wherein the third plurality of connectors are bonded to the second plurality of conductive studs.

7. The PoP device of claim 6 , wherein the second package structure comprises:
a plurality of stacked dynamic random access memory (DRAM) chips;
a second package substrate bonded to the plurality of stacked DRAM chips; and
a third molding compound encasing the plurality of stacked DRAM chips.

8. The PoP device of claim 5 , wherein lateral surfaces of the first package structure and the second molding compound are substantially level.

9. The PoP device of claim 1 , wherein the logic chip is an application processor, and wherein the memory chip is a wide input/output (IO) chip.

10. A package comprising:
a first die comprising first contact pads and second contact pads at a first surface of the first die;
a second die bonded to the second contact pads of the first die, wherein a portion of the first die extends laterally past the second die, and wherein the first contact pads are disposed on the portion of the first die;
first conductive studs adjacent the second die and disposed on the first contact pads;
a first molding compound extending along sidewalls of the second die, wherein the first conductive studs extend through the first molding compound;
fan-out redistribution layers (RDLs) on an opposing side of the second die as the first die, wherein the fan-out RDLs are electrically connected to the first conductive studs;
second connectors disposed on an opposing side of the fan-out RDLs as the second die, wherein the second connectors are electrically connected to the fan-out RDLs;
a package substrate bonded to the second die by the second connectors, wherein the package substrate comprises second contact pads disposed on a same surface of the package substrate as the second connectors;
second conductive studs disposed on the second contact pads; and
a second molding compound encircling the first die, the second die, the first molding compound, the first conductive studs, the fan-out RDLs, and the second connectors, wherein the second conductive studs extend through the second molding compound.

11. The package of claim 10 further comprising a package structure bonded to the second conductive studs, wherein the package structure is disposed on an opposing side of the first die as the package substrate.

12. The package of claim 10 , wherein the second molding compound contacts a sidewall of the first die.

13. The package of claim 11 , wherein the package structure comprises:
a plurality of stacked dynamic random access memory (DRAM) chips;
a second package substrate bonded to the plurality of stacked DRAM chips; and
a third molding compound encasing the plurality of stacked DRAM chips.

14. The package of claim 11 , wherein the package structure is a low-power double data rate (LP-DDR) 2 package or a LP-DDR3 package.

15. The package of claim 10 , wherein the first die is an application processor, and wherein the second die is a wide input/output (IO) chip.

16. The package of claim 10 , wherein top surfaces of the second conductive studs and the second molding compound are substantially level.

17. A package comprising:
a first package structure comprising:
a first die bonded to a second die by a first plurality of connectors, active surfaces of the first die and the second die facing each other;
a first molding compound encircling the second die; and
a first plurality of conductive studs laterally adjacent the second die and the first plurality of connectors, the first plurality of conductive studs contacting contact pads on the first die, the first plurality of conductive studs extending through the first molding compound from a first plane to the contact pads of the first die, the first plane being level with a backside surface of the second die; and
one or more redistribution layers (RDLs) on a surface of the second die opposite the first die;

a first package substrate; and
a second plurality of connectors bonding the first package structure to the first package substrate, the second plurality of connectors being disposed on a surface of the one or more RDLs opposite the second die.

18. The package of claim 17 , wherein an entirety of the first plurality of conductive studs are disposed in the first molding compound.

19. The package of claim 17 further comprising:
a second molding compound encircling the first package structure; and
a second plurality of conductive studs adjacent the first die and the second die, the second plurality of conductive studs extending through the second molding compound and being attached to contact pads on the first package substrate.

20. The package of claim 19 further comprising:
a second package structure; and
a third plurality of connectors bonding the second package structure to the first package substrate, the third plurality of connectors being coupled to the second plurality of conductive studs.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yee Kuo-Chung
• Lii Mirng-Ji
• Lee Chien-Hsun
• Wu Jiun Yi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title