Semiconductor device

Patent metadata

Field	Value
Publication number	US-9449654-B2
Application number	US-201414328552-A
Country	US
Kind code	B2
Filing date	Jul 10, 2014
Priority date	Feb 23, 2011
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first memory;
a second memory;
a third memory;
a fourth memory;
a substrate that includes:
a first layer that includes a wiring pattern formed on a first surface of the substrate,
a second layer that includes a wiring pattern formed on a second surface of the substrate,
a third layer, provided between the first layer and the second layer, on which a wiring pattern is formed, and
a connector that includes electrodes, to be connected with a host device, formed on the second layer of the substrate;

a controller configured to control operations of the first, second, third, and fourth memories, wherein the controller is mounted on the first layer of the substrate; and
a first signal line configured to connect the controller with the connector, the first signal line including:
a first portion disposed on the first layer of the substrate and extending from the controller,
a second portion that penetrates through the substrate from the first layer to the second layer, and
a third portion disposed on the second layer of the substrate and connected with the electrodes of the connector.

2. The semiconductor device according to claim 1 , wherein the substrate includes:
a pair of long sides; and
a pair of short sides that are orthogonal to the long sides in a plan view, wherein
the first, second, third, and fourth memories are configured to be arranged along the pair of long sides.

3. The semiconductor device according to claim 2 , wherein
the first and second memories are arranged along one of the pair of the long sides of the substrate; and
the third and fourth memories are arranged along the other one of the pair of the long sides of the substrate.

4. The semiconductor device according to claim 1 , further comprising:
a temperature sensor configured to measure a temperature of at least one of the first, second, third, and fourth memories.

5. The semiconductor device according to claim 1 , further comprising:
a second signal line configured to connect the controller with the first, second, third, and fourth memories, the second signal line including a portion disposed in the third layer.

6. The semiconductor device according to claim 1 , wherein the first signal line configured to connect the controller with the connector further includes a portion disposed on the third layer.

7. The semiconductor device according to claim 1 , further comprising:
a first resistive element configured to be disposed in the vicinity of the first memory,
a second resistive element configured to be disposed in the vicinity of the second memory,
a third resistive element configured to be disposed in the vicinity of the third memory, and,
a fourth resistive element configured to be disposed in the vicinity of the fourth memory.

8. The semiconductor device according to claim 1 , wherein
most of the area of the second layer of the substrate, except for a region provided with the first signal line, is a ground pattern.

9. The semiconductor device according to claim 1 , wherein:
the third layer comprises a first inner layer including an overlapping portion which overlaps with the first signal line, and nearly no wiring patterns are formed in the overlapping portion.

10. The semiconductor device according to claim 1 , wherein
the first signal line is partially broken on the first layer.

11. The semiconductor device according to claim 10 , further comprising:
a relay terminal provided on the broken portion of the first signal line.

12. The semiconductor device according to claim 1 , further comprising:
first to fourth wiring lines connecting the first to fourth memories to the controller, respectively;
a first resistive element configured to be provided in the first wiring line,
a second resistive element configured to be provided in the second wiring line,
a third resistive element configured to be provided in the third wiring line, and
a fourth resistive element configured to be provided in the fourth wiring line.

13. The semiconductor device according to claim 7 , wherein
the first wiring line is connected to the resistive element through a via-hole.

14. The semiconductor device according to claim 7 , wherein
the first wiring line is connected to the controller on the first layer of the substrate, extends through a first via hole to an inner layer, has a portion which extends on the inner layer, extends through a second via hole, and is connected to the first resistive element.

15. The semiconductor device according to claim 7 , wherein
a first portion of the first wiring line connecting the first resistive element to the first memory is shorter than a second portion of the first wiring line connecting the controller to the first resistive element.

16. The semiconductor device according to claim 7 , wherein
a first portion of the first wiring line connecting the first resistive element to the first memory is shorter than a second portion of the first wiring line connecting the controller to the first resistive element,
a first portion of the second wiring line connecting the second resistive element to the second memory is shorter than a second portion of the second wiring line connecting the controller to the second resistive element,
a first portion of the third wiring line connecting the third resistive element to the third memory is shorter than a second portion of the third wiring line connecting the controller to the third resistive element, and
a first portion of the fourth wiring line connecting the fourth resistive element to the fourth memory is shorter than a second portion of the fourth wiring line connecting the controller to the fourth resistive element.

17. The semiconductor device according to claim 7 , wherein
a height of the first resistive element is lower than a height of the first memory,
a height of the second resistive element is lower than a height of the second memory,
a height of the third resistive element is lower than a height of the third memory, and
a height of the fourth resistive element is lower than a height of the fourth memory.

18. The semiconductor device according to claim 7 , wherein
a region of the first, second, third, and fourth resistive elements is lower than a region of the first, second, third, and fourth memories.

19. The semiconductor device according to claim 1 , further comprising:
a power supply circuit configured to be disposed near the connector, the power supply circuit being configured to bypass the first signal line.

20. The semiconductor device according to claim 1 , wherein
the first portion of the first signal line is shorter than the third portion of the first signal line.

21. The semiconductor device according to claim 1 , further comprising:
a fifth memory facing the first memory,
a sixth memory facing the second memory,
a seventh memory facing the third memory, and
an eighth memory facing the fourth memory.

22. The semiconductor device according to claim 21 , wherein
the first memory and the fifth memory are connected to a first resistive element by a wiring line.

23. The semiconductor device according to claim 22 , wherein
operation of each of the first memory and the fifth memory is determined on the basis of whether a channel enable signal is active or not.

24. The semiconductor device according to claim 1 , wherein
ball-shaped electrodes are

Assignees

• Toshiba Kk

Inventors

• Sugita Masato
• Kimura Naoki
• Kimura Daisuke

Classifications

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G06F2213/0032

  Serial ATA [SATA] · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title