Array substrate, manufacturing method thereof, and flat panel display device

Patent metadata

Field	Value
Publication number	US-9210797-B2
Application number	US-201313985285-A
Country	US
Kind code	B2
Filing date	Jul 1, 2013
Priority date	Jun 24, 2013
Publication date	Dec 8, 2015
Grant date	Dec 8, 2015

Abstract

Any one of the fan-out leads includes a first metal strip portion having a predetermined number, located on a glass substrate, disposed along an extension direction of the fan-out lead and is spaced apart; an insulation layer covering each of the first metal strip portion, and disposed with a first through hole and a second through hole; and a second metal strip portion located on the insulation layer and being contacted with each of the first metal strip portion by the first through hole and the second through hole. Wherein, the lengths of the first metal strip portions of the fan-out leads are gradually increased along the direction which is from the center to the edge of the fan shape such that impedances of the fan-out leads are consistent.

First claim

What is claimed is:

1. An array substrate comprising
an effective display region; and
a non-effective display region surrounding the effective display region and having multiple fan-out leads distributed as a fan shape, wherein, each fan-out lead has a predetermined length, and the predetermined lengths of the multiple fan-out leads are increased along a direction which is from a center to an edge of the fan shape, wherein, any one of the fan-out leads comprises:
a first metal strip portion having a predetermined number, wherein, the first metal strip portion having the predetermined number disposed along an extension direction of the fan-out lead and is spaced apart, and a length of each of the first metal strip portion is less than or equal to the predetermined length;
an insulation layer covering each of the first metal strip portion, and a location of the insulation layer which is covering each of the first metal strip portion is disposed with a first through hole and a second through hole; and
a second metal strip portion located on the insulation layer and being contacted with each of the first metal strip portion by the first through hole and the second through hole, wherein, a length of the second metal strip portion is equal to the predetermined length;
wherein, the lengths of the first metal strip portions of the fan-out leads are gradually increased along the direction which is from the center to the edge of the fan shape and the predetermined numbers of the first metal strip portions are gradually decreased along the direction such that impedances of the fan-out leads are consistent; and
wherein, the length of each of the first metal strip portion is equal.

2. The array substrate according to claim 1 , wherein, any one of the fan-out leads comprises a passivation layer covering the second metal strip portion.

3. The array substrate according to claim 1 , wherein, a distance between each of the first metal strip portion is equal.

4. The array substrate according to claim 1 , wherein, a line width of each of the fan-out leads is equal.

5. A flat panel display device comprising an array substrate, wherein the array substrate comprises:
an effective display region; and
a non-effective display region surrounding the effective display region and having multiple fan-out leads distributed as a fan shape, wherein, each fan-out lead has a predetermined length, and the predetermined lengths of the multiple fan-out leads are increased along a direction which is from a center to an edge of the fan shape, wherein, any one of the fan-out leads comprises:
a first metal strip portion having a predetermined number, wherein, the first metal strip portion having the predetermined number disposed along an extension direction of the fan-out lead and is spaced apart, and a length of each of the first metal strip portion is less than or equal to the predetermined length;
an insulation layer covering each of the first metal strip portion, and a location of the insulation layer which is covering each of the first metal strip portion is disposed with a first through hole and a second through hole; and
a second metal strip portion located on the insulation layer and being contacted with each of the first metal strip portion by the first through hole and the second through hole, wherein, a length of the second metal strip portion is equal to the predetermined length;
wherein, the lengths of the first metal strip portions of the fan-out leads are gradually increased along the direction which is from the center to the edge of the fan shape and the predetermined numbers of the first metal strip portions are gradually decreased along the direction such that impedances of the fan-out leads are consistent; and
wherein, the length of each of the first metal strip portion is equal.

6. The flat panel display device according to claim 5 , wherein, any one of the fan-out leads comprises a passivation layer covering the second metal strip portion.

7. The flat panel display device according to claim 5 , wherein, a distance between each of the first metal strip portion is equal.

8. The flat panel display device according to claim 5 , wherein, a line width of each of the fan-out leads is equal.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelect

Inventors

• Chai Li

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/85

  characterised by only passive components · CPC title