Delta sigma modulator with modified DWA block

Patent metadata

Field	Value
Publication number	US-9716514-B2
Application number	US-201615160116-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	May 22, 2015
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

First claim

What is claimed is:

1. A delta sigma modulator comprising:
a summer configured to generate an error signal in response to an input signal and a feedback signal;
a loop filter coupled to the summer and configured to generate a filtered signal in response to the error signal;
a quantizer coupled to the loop filter and configured to generate a quantized output signal in response to the filtered signal;
a digital to analog converter (DAC) coupled to the summer, and configured to generate the feedback signal in response to a plurality of selection signals; and
a modified data weighted averaging (DWA) block coupled between the quantizer and the DAC, the modified DWA block configured to receive a clock signal and configured to generate the plurality of selection signals in response to the quantized output signal and a primary coefficient, wherein the primary coefficient varies with the clock signal.

2. The delta sigma modulator of claim 1 , wherein a first quantized output signal is generated at a first clock cycle and a second quantized output signal is generated at a second clock cycle, wherein the clock signal comprises the first clock cycle and the second clock cycle.

3. The delta sigma modulator of claim 1 further comprising a reset filter coupled to the quantizer and configured to generate a digital output signal in response to the quantized output signal and a plurality of filter coefficients.

4. The delta sigma modulator of claim 3 , wherein a primary coefficient at a clock signal is derived from the plurality of filter coefficients.

5. The delta sigma modulator of claim 3 , wherein the reset filter is configured to sum a product of the first quantized output signal and a first filter coefficient and a product of the second quantized output signal and a second filter coefficient to generate the digital output signal, wherein the plurality of filter coefficients comprises the first filter coefficient and the second filter coefficient.

6. The delta sigma modulator of claim 1 , wherein the modified DWA block comprises:
a plurality of multipliers configured to generate a plurality of intermediate signals, each multiplier configured to multiply a selection signal of the plurality of selection signals and the primary coefficient to generate an intermediate signal of the plurality of intermediate signals;
a plurality of primary filters coupled to the plurality of multipliers, each primary filter coupled to a multiplier of the plurality of multipliers, the plurality of primary filters configured to generate a plurality of element selector signals in response to the plurality of intermediate signals; and
a sorter coupled to the plurality of primary filters, and configured to sort the plurality of element selector signals to generate the plurality of selection signals.

7. The delta sigma modulator of claim 6 , wherein a number of selection signals of the plurality of selection signals generated by the modified DWA block is based on the quantized output signal.

8. The delta sigma modulator of claim 6 , wherein when the quantized output signal is the first quantized output signal generated at the first clock cycle, the primary coefficient is equal to the first filter coefficient.

9. The delta sigma modulator of claim 1 , wherein the DAC comprises a plurality of DAC elements, each DAC element of the plurality of DAC elements configured to be activated by a selection signal of the plurality of selection signals.

10. The delta sigma modulator of claim 9 , wherein a number of DAC elements in the DAC are proportional to a number of bits in the quantized output signal.

11. The delta sigma modulator of claim 9 , wherein an element selector signal of the plurality of element selector signals represents in-band component of DAC element selection sequence.

12. A method comprising:
generating an error signal in response to an input signal and a feedback signal;
generating a filtered signal in response to the error signal;
generating a quantized output signal in response to the filtered signal;
generating the feedback signal by a digital to analog converter (DAC) in response to a plurality of selection signals; and
generating the plurality of selection signals in response to the quantized output signal and a primary coefficient, wherein the primary coefficient varies with a clock signal.

13. The method of claim 12 further comprising generating a first quantized output signal at a first clock cycle, and generating a second quantized output signal at a second clock cycle, wherein the clock signal comprises the first clock cycle and the second clock cycle.

14. The method of claim 12 further comprising generating a digital output signal in response to the quantized output signal and a plurality of filter coefficients.

15. The method of claim 14 , wherein a primary coefficient at a clock signal is derived from the plurality of filter coefficients.

16. The method of claim 14 further comprising summing a product of the first quantized output signal and a first filter coefficient and a product of the second quantized output signal and a second filter coefficient to generate the digital output signal, wherein the plurality of filter coefficients comprises the first filter coefficient and the second filter coefficient.

17. The method of claim 12 , wherein generating the feedback signal further comprises:
generating a plurality of intermediate signals, an intermediate signal of the plurality of intermediate signals is generated by multiplying a selection signal of the plurality of selection signals and the primary coefficient;
generating a plurality of element selector signals in response to the plurality of intermediate signals;
sorting the plurality of element selector signals to generate the plurality of selection signals; and
activating a first set of DAC elements in the DAC in response to the plurality of selection signals, wherein the DAC includes the first set of DAC element and a second set of DAC elements.

18. The method of claim 17 , wherein a number of DAC elements in the first set of DAC elements is based on the quantized output signal.

19. A device comprising:
a sensor configured to generate an input signal in response to a real-world signal;
a processor coupled to the sensor and configured to process a digital output signal; and
a delta sigma modulator coupled between the sensor and the processor and configured to generate the digital output signal, the delta sigma modulator comprising:
a summer configured to generate an error signal in response to the input signal and a feedback signal;
a loop filter coupled to the summer and configured to generate a filtered signal in response to the error signal;
a quantizer coupled to the loop filter and configured to generate a quantized output signal in response to the filtered signal;
a digital to analog converter (DAC) coupled to the summer, and configured to generate the feedback signal in response to a plurality of selection signals; and
a modified data weighted averaging (DWA) block coupled between the quantizer and the DAC, the modified DWA block configured to receive a clock signal and configured to generate the plurality of selection signals in response to the quantized output signal and a primary coefficient, wherein the primary coefficient varies with the clock signal.

20. The device of claim 19 , wherein the delta sigma modulator further comprises a reset filter coupled to the quantizer and configured to generate the digital output signal in response to th

Assignees

• Texas Instruments Inc

Inventors

• Miglani Eeshan
• Gunasekaran Karthikeyan

Classifications

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M1/0665

  using data dependent selection of the elements, e.g. data weighted averaging · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title