Charge-sharing and charge-redistribution DAC and method for successive approximation analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-9954549-B2
Application number	US-201715595045-A
Country	US
Kind code	B2
Filing date	May 15, 2017
Priority date	Jul 8, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.

First claim

What is claimed is:

1. A hybrid digital-to-analog converter comprising:
a charge-sharing digital-to-analog converter configured to receive a digital input signal having a plurality of bits, wherein the plurality of bits include a most-significant-bit and a least-significant-bit, wherein the charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit; and
a charge redistribution digital-to-analog converter configured to convert the least-significant-bit to provide a second portion of the analog signal, wherein the charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.

2. The digital-to-analog converter of claim 1 , wherein:
the charge-sharing digital-to-analog converter is configured to selectively charge the first capacitors based on an input voltage of the digital input signal during a sampling phase of the digital input signal; and
the charge redistribution digital-to-analog converter is configured to selectively charge the second capacitors based on a common mode voltage during the sampling phase of the digital input signal.

3. The hybrid digital-to-analog converter of claim 1 , wherein:
the most-significant-bit is one of a plurality of most-significant-bits of the plurality of bits;
the least-significant-bit is one of a plurality of least-significant-bits of the plurality of bits;
the charge-sharing digital-to-analog converter is configured to convert the plurality of most-significant-bits to provide a third portion of the analog signal; and
the charge redistribution digital-to-analog converter is configured to convert the plurality of least-significant-bits a fourth portion of the analog signal.

4. The hybrid digital-to-analog converter of claim 1 , wherein circuits of the charge-sharing digital-to-analog converter corresponding to the plurality of bits are binary weighted such that capacitance weighting for each of the plurality of bits is a product of 2 bit#-1 and a capacitance weighting for the most-significant-bit.

5. The hybrid digital-to-analog converter of claim 1 , wherein circuits of the charge-sharing digital-to-analog converter corresponding to the plurality of bits are non-binary weighted such that capacitance weighting for each of the plurality of bits is not a product of 2 bit#-1 and a capacitance weighting for a most-significant-bit.

6. The hybrid digital-to-analog converter of claim 1 , wherein circuits of the charge redistribution digital-to-analog converter corresponding to the plurality of bits are binary weighted such that capacitance weighting for each of the plurality of bits is a product of 2 bit#-1 and a capacitance weighting for the least-significant-bit.

7. The hybrid digital-to-analog converter of claim 1 , wherein circuits of the charge redistribution digital-to-analog converter corresponding to the plurality of bits are non-binary weighted such that capacitance weighting for each of the plurality of bits is not a product of 2 bit#-1 and a capacitance weighting for a least significant bit.

8. The hybrid digital-to-analog converter of claim 1 , wherein:
the charge-sharing digital-to-analog converter comprises a differential output; and
the charge redistribution digital-to-analog converter comprises
a differential input connected to the differential output of the first digital-to-analog converter, and
a differential output providing the analog signal.

9. The hybrid digital-to-analog converter of claim 1 , wherein:
the most-significant-bit is one of a plurality of most-significant-bits;
the least-significant-bit is one of a plurality of least-significant-bits;
the plurality of bits comprise the plurality of most-significant-bits and the plurality of least-significant-bits;
the charge-sharing digital-to-analog converter comprises a first plurality of bit circuits;
each of the first plurality of bits circuits converts a corresponding one of the plurality of most-significant-bits into a respective portion of the analog signal;
the charge redistribution digital-to-analog converter comprises a second plurality of bit circuits; and
each of the second plurality of bits circuits converts a corresponding one of the plurality of least-significant-bits into a respective portion of the analog signal.

10. An analog-to-digital converter comprising:
the hybrid digital-to-analog converter of claim 1 ; and
an amplifier or integrator configured to amplify or integrate the analog signal;
a latch configured to latch an output of the amplifier or integrator; and
a successive approximation module configured to (i) receive an output of the latch, and (ii) perform successive approximations of the plurality of bits to generate a digital output signal.

11. A digital-to-analog converter comprising:
the hybrid digital-to-analog converter of claim 1 , wherein the least-significant-bit is a first least-significant-bit; and
a third digital-to-analog converter configured to convert a second least-significant-bit of the plurality of bits.

12. An analog-to-digital converter comprising:
a first analog-to-digital converter including
the hybrid digital-to-analog converter of claim 1 , wherein the least-significant-bit is a first least-significant-bit, and
a first control module configured to generate a first digital signal based on the analog signal; and

a second analog-to-digital converter including
a third digital-to-analog converter configured to convert a second least-significant-bit of the plurality of bits, and
a second control module configured to generate a second digital signal based on an output of the third digital-to-analog converter,

wherein the second analog-to-digital converter performs a fine conversion relative to the first analog-to-digital converter.

13. The analog-to-digital converter of claim 12 , further comprising:
a decimation filter configured to filter the second digital signal; and
a combination module configured to combine the first digital signal and an output of the decimation filter to provide a resultant output signal.

14. An analog-to-digital converter comprising:
a digital-to-analog converter including
the hybrid digital-to-analog converter of claim 1 , wherein the least-significant-bit is a first least-significant-bit, and
a third digital-to-analog converter configured to convert a second least-significant-bit of the digital input signal to a provide a third portion of the analog signal;

a control module configured to generate a first digital signal based on the analog signal;
a decimation filter configured to filter a digital output of the control module; and
a combination module configured to combine the first digital signal and an output of the decimation filter to provide a resultant output signal.

15. A method comprising:
receiving a digital input signal having a plurality of bits at a charge-sharing digital-to-analog converter, wherein the plurality of bits include a most-significant-bit and a least-significant-bit;
converting the most-significant-bit via the charge-sharing digital-to-analog converter to provide a first portion of an analog signal;
selectively sharing charges of first capacitors of the charge-sharing digital-to-analog converter during a successive approximation of the most-significant-bit;
converting the least-significant-bit via a charge redist

Assignees

• Marvell World Trade Ltd

Inventors

• Venca Alessandro
• Nani Claudio
• Ghittori Nicola
• Bosi Alessandro

Classifications

• H03M1/1009

  Calibration · CPC title

• H03M1/667 Primary

  Recirculation type · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/08

  of noise {(H03M1/0617 takes precedence)} · CPC title