Gain calibration for ADC with external reference

Patent metadata

Field	Value
Publication number	US-9584150-B2
Application number	US-201514793118-A
Country	US
Kind code	B2
Filing date	Jul 7, 2015
Priority date	Jul 7, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC), comprising:
a passive sample and hold (SH) capacitance arranged to receive an analog input voltage;
a digital-to-analog converter (DAC) capacitance coupled to the SH capacitance at a first node and switchably coupled to a reference voltage at another node of the DAC capacitor;
a calibration capacitance coupled at the first node, the calibration capacitance adjustable to minimize a difference between a capacitance value of the SH capacitance and a capacitance value comprising a sum of the calibration capacitance and the DAC capacitance; and
a calibration logic controller configured to:
couple the SH capacitance to the reference voltage at another node of the SH capacitance;
couple the first node to a bias voltage;
couple the DAC capacitance to ground at the other node of the DAC capacitance;
disconnect the SH capacitance from the reference voltage and the DAC capacitance from ground and setting the first node to a high impedance state after charging the SH capacitance with the reference voltage;
couple the SH capacitance to ground at the other node of the SH capacitance;
couple the DAC capacitance to the reference voltage at the other node of the DAC capacitance;
compare an injected voltage from the SH capacitance to an injected voltage from the DAC capacitance at the first node;
place a comparator coupled to the first node on a trip point of the comparator when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are equal; and
detect a sign of a voltage magnitude deviation between the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance, and add or subtract a capacitance from the calibration capacitance when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are not equal.

2. The ADC of claim 1 , wherein the comparator is coupled at the first node and a successive approximation register (SAR) coupled to an output of the comparator, an output of the SAR comprising a digital output of the ADC.

3. The ADC of claim 2 , wherein the DAC capacitance comprises an array of multiple switched capacitances, the ADC further comprising a calibration logic module arranged to receive the output of the SAR and to adjust the calibration capacitance based on how many of the multiple capacitances of the DAC capacitance are switched to the reference voltage.

4. The ADC of claim 1 , wherein the calibration capacitance is arranged to track the DAC capacitance and to reduce or eliminate a deviation between a capacitance value of the DAC capacitance and a capacitance value of the SH capacitance.

5. The ADC of claim 1 , wherein the ADC does not implement a buffer.

6. The ADC of claim 1 , wherein the calibration capacitance is arranged to reduce or eliminate a gain error and a linear error of the ADC.

7. The ADC of claim 1 , wherein the calibration capacitance comprises an array of multiple capacitances having a total capacitance value that is greater than a difference between a capacitance value of the SH capacitance and a capacitance value of the DAC capacitance.

8. The ADC of claim 1 , wherein a single capacitance array is used as the SH capacitance and the DAC capacitance.

9. An analog-to-digital converter (ADC), comprising:
a passive sample and hold (SH) capacitance arranged to receive an analog input voltage;
a digital-to-analog converter (DAC) capacitance comprising an array of multiple switched capacitances, coupled to the SH capacitance at a first node and switchably coupled to a reference voltage at another node of the DAC;
a comparator coupled at the first node at an input of the comparator;
a successive approximation register (SAR) coupled to an output of the comparator, an output of the SAR comprising a digital output of the ADC;
a calibration capacitance coupled at the first node, the calibration capacitance adjustable to minimize a difference between a capacitance value of the SH capacitance and a capacitance value comprising a sum of the calibration capacitance and the DAC capacitance; and
a calibration logic module configured to:
couple the SH capacitance to the reference voltage at another node of the SH capacitance;
couple the first node to a bias voltage;
couple the DAC capacitance to ground at the other node of the DAC capacitance;
disconnect the SH capacitance from the reference voltage and the DAC capacitance from ground and setting the first node to a high impedance state after charging the SH capacitance with the reference voltage;
couple the SH capacitance to ground at the other node of the SH capacitance;
couple the DAC capacitance to the reference voltage at the other node of the DAC capacitance;
compare an injected voltage from the SH capacitance to an injected voltage from the DAC capacitance at the first node;
place the comparator coupled to the first node on a trip point of the comparator when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are equal; and
detect a sign of a voltage magnitude deviation between the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance, and add or subtract a capacitance from the calibration capacitance when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are not equal.

10. The ADC of claim 9 , further comprising an up-down counter arranged to derive a gain calibration value used by the calibration logic module to adjust the calibration capacitance.

11. The ADC of claim 10 , wherein the up-down counter is increased or decreased after a calibration step, tracking a gain error of the ADC based on a difference in capacitance values of the SH capacitance and the DAC capacitance.

12. The ADC of claim 10 , wherein the calibration capacitance comprises an array of multiple switched capacitances, and wherein an output of the up-down counter triggers a switching of one or more capacitances of the calibration capacitance to or from the reference voltage, based on a switching of one or more capacitances of the DAC capacitance to or from the reference voltage.

13. The ADC of claim 10 , further comprising an arithmetic unit arranged to calculate a final calibration value used by the calibration logic module to adjust the calibration capacitance, the final calibration value comprising the gain calibration value and a derived linearity calibration value.

14. The ADC of claim 13 , wherein the linearity calibration value is derived by comparing a capacitance value of an identified capacitance representing an associated bit position with a sum of capacitance values of capacitances representing all lesser bit positions from the associated bit position.

15. The ADC of claim 9 , further comprising a coupling capacitor coupled between the calibration capacitance and the first node and arranged to scale the calibration capacitance down with respect to the DAC capacitance.

16. A method, comprising:
forming an analog-to-digital converter (ADC), including:
coupling a passive sample and hold (SH) capacitance to a digital-to-analog converter (DAC) capacitance at a first node;
coupling the SH capacitance to an input voltage of the ADC at another node of the SH capacitance; and
coupling the DAC capacitance to a reference voltage at another node of the DAC capacitance;

coupling a calibration capacitance at the first node;
comparing an injected voltage from the SH capacitance to an injected voltage from the DAC capacitance at the first node; a

Assignees

• Infineon Technologies Ag

Inventors

• Bogner Peter

Classifications

• H03M1/1009

  Calibration · CPC title

• H03M1/468 Primary

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/0678

  using additional components or elements, e.g. dummy components · CPC title

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title