Tapered gate oxide in LDMOS devices

Patent metadata

Field	Value
Publication number	US-10050115-B2
Application number	US-201414585933-A
Country	US
Kind code	B2
Filing date	Dec 30, 2014
Priority date	Dec 30, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a channel region in a first well in a substrate;
a drift region in a second well in the substrate;
a gate dielectric comprising:
a first portion having a first planar upper surface and first uniform thickness;
a second portion having a second planar upper surface and a second uniform thickness different than the first uniform thickness; and
a transition portion having tapered surface extending from the first portion to the second portion,

wherein the gate dielectric is on a planar upper surface of the substrate, and
the tapered surface is at an acute angle relative to the upper surface of the substrate,
further comprising a shallow trench isolation structure that abuts each of the first well, the second well, and a bottom surface of the gate dielectric,
wherein the gate dielectric comprises a flat bottom surface that contacts the shallow trench isolation structure, the first well, and the second well, and
the shallow trench isolation structure comprises a flat uppermost surface that contacts the flat bottom surface of the gate dielectric.

2. The structure of claim 1 , wherein the tapered surface extends from the first planar upper surface to the second planar upper surface.

3. The structure of claim 1 , wherein:
the first uniform thickness is greater than the second uniform thickness; and
the first portion is on a drift region of a laterally diffused metal oxide semiconductor (LDMOS) device.

4. The structure of claim 3 , wherein the second portion is on the channel region of the LDMOS device, and further comprising:
a gate conductor on the gate dielectric;
a source region abutting the channel region; and
the drain region abutting the drift region.

5. The structure of claim 1 , wherein the gate dielectric is part of a laterally diffused metal oxide semiconductor (LDMOS) field effect transistor (FET) that is formed without a field oxide.

6. The structure of claim 3 , further comprising a gate conductor on and covering an entirety of an uppermost surface of the first portion.

7. The structure of claim 1 , further comprising:
a gate conductor on and covering the first portion, the second portion, and the transition portion; and
sidewall spacers contacting vertical sidewalls of the gate conductor and the gate dielectric.

8. The structure of claim 1 , wherein the flat uppermost surface of the shallow trench isolation structure is coplanar with an upper surface of the first well and an upper surface of the second well.

9. The structure of claim 8 , further comprising:
a gate conductor on and covering the first portion, the second portion, and the transition portion of the gate dielectric;
a first sidewall spacer contacting first vertical sidewalls of the gate conductor and the gate dielectric; and
a second sidewall spacer contacting second vertical sidewalls of the gate conductor and the gate dielectric.

10. A semiconductor structure, comprising:
a channel region in a first well in a substrate;
a drift region in a second well in the substrate;
a source region in the substrate and abutting the channel region;
a drain region in the substrate and abutting the drift region;
a gate dielectric comprising:
a thin portion on the channel region;
a thick portion on the drift region; and
a transition region having tapered surface extending from the thin portion to the thick portion,

wherein the gate dielectric is on a planar upper surface of the substrate, and
the tapered surface is at an acute angle relative to the upper surface of a substrate,
further comprising a shallow trench isolation structure that abuts each of the first well, the second well, and a bottom surface of the gate dielectric,
wherein the shallow trench isolation structure abuts and extends underneath each of the thick portion, the thin portion, and the transition region,
the gate dielectric comprises a flat bottom surface that contacts the shallow trench isolation structure, the first well, and the second well, and
the shallow trench isolation structure comprises a flat uppermost surface that contacts the flat bottom surface of the gate dielectric, and that is coplanar with an upper surface of the first well and an upper surface of the second well.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Brown Brennan J
• Feilchenfeld Natalie B
• Levy Max G
• Sharma Santosh
• Shi Yun
• Zierak Michael J

Classifications

• H10D64/01332 Primary

  Making the insulator · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H01L29/66681

  Electricity · mapped topic

• H01L29/42368 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic