High-voltage LDMOS integrated device

Patent metadata

Field	Value
Publication number	US-9236469-B2
Application number	US-201314089906-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Nov 28, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

The invention discloses a high-voltage LDMOS integrated device, which is interdigitally structured in a plan view and which including: a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area particularly includes: a first drain; and a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and a second area non-overlapping with the first area, wherein a second sectional structure of the second area particularly includes: a second drain; and a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well.

First claim

What is claimed is:

1. A high-voltage LDMOS integrated device, interdigitally structured in a plan view, comprising:
a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area includes:
a first drain; and
a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and

a second area non-overlapping with the first area, wherein a second sectional structure of the second area includes:
a second drain; and
a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well, wherein the second low-voltage N-well is located in the second deep-N well, and the second deep-N well is located in the P-type substrate.

2. The high-voltage LDMOS integrated device according to claim 1 , wherein the first sectional structure further includes:
a first body area located in the P-type substrate and consisted of a first P-well.

3. The high-voltage LDMOS integrated device according to claim 1 , wherein the second sectional structure further includes:
a second body area located in the P-type substrate and consisted of a second P-well.

4. The high-voltage LDMOS integrated device according to claim 1 , wherein the first sectional structure further includes:
a first transversal voltage-withstanding buffer layer consisted of the P-type substrate, a first high-voltage N-well located in the P-type substrate and the first low-voltage N-well.

5. The high-voltage LDMOS integrated device according to claim 1 , wherein the second sectional structure further includes:
a second transversal voltage-withstanding buffer layer consisted of a second high-voltage N-well located in the P-type substrate and the second low-voltage N-well.

6. The high-voltage LDMOS integrated device according to claim 1 , further comprising a gate oxide layer formed in a third area on the first area and the second area.

7. The high-voltage LDMOS integrated device according to claim 6 , further comprising a field oxide layer formed in a fourth area non-overlapping with the third area, wherein the fourth area belongs to the first area or the second area.

8. The high-voltage LDMOS integrated device according to claim 7 , further comprising a poly-silicon gate formed in a fifth area on the third area or the fourth area.

9. The high-voltage LDMOS integrated device according to claim 8 , further comprising P+ and N+ sources formed below the gate oxide layer in the third area non-overlapping with the fifth area.

Assignees

• Univ Peking Founder Group Co
• Founder Microelectronics Internat Co Ltd

Inventors

• Pan Guangran
• Shi Jincheng
• Gao Zhenjie
• Wen Yan

Classifications

• H10D62/051

  Forming charge compensation regions, e.g. superjunctions · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title