Semiconductor structure and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10049890-B2
Application number	US-201615261393-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Sep 9, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

The present disclosure provides a semiconductor structure, comprising a substrate, dielectric layers and conductive layers. A first dielectric layer is disposed on a bottom surface and sidewall surfaces of a filled trench of the substrate. A first conductive layer is disposed on the first dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A second dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the second dielectric layer and has a first surface in the filled trench and a second surface above the substrate. A third dielectric layer is disposed on the second conductive layer. A third conductive layer is disposed in the filled trench and on the third dielectric layer. A top surface of the third conductive layer is lower than the second surface of the second conductive layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate having a filled trench;
a first dielectric layer disposed on a bottom surface and sidewall surfaces of the filled trench and on the substrate;
a first conductive layer disposed on the first dielectric layer, the first conductive layer having a first surface in the filled trench and a second surface above the substrate;
a second dielectric layer disposed on the first conductive layer;
a second conductive layer disposed on the second dielectric layer, the second conductive layer having a first surface in the filled trench and a second surface above the substrate;
a third dielectric layer disposed on the second conductive layer; and
a third conductive layer disposed in the filled trench and on the third dielectric layer,
wherein a top surface of the third conductive layer is lower than the second surface of the second conductive layer.

2. The semiconductor structure of claim 1 , wherein the top surface of the third conductive layer is lower than the second surface of the first conductive layer.

3. The semiconductor structure of claim 1 , wherein the top surface of the third conductive layer is higher than a top surface of the substrate.

4. The semiconductor structure of claim 1 , further comprising:
a first conductive contact electrically connected to the second surface of the first conductive layer;
a second conductive contact electrically connected to the second surface of the second conductive layer; and
a third conductive contact electrically connected to the top surface of the third conductive layer.

5. The semiconductor structure of claim 4 , wherein a length of the third conductive contact is longer than a length of the second conductive contact.

6. The semiconductor structure of claim 4 , wherein a length of the third conductive contact is longer than a length of the first conductive contact.

7. The semiconductor structure of claim 1 , wherein the first conductive layer, the second conductive layer and the third conductive layer comprise polysilicon.

8. The semiconductor structure of claim 1 , further comprising:
a first silicide disposed on the second surface of the first conductive layer;
a second silicide disposed on the second surface of the second conductive layer; and
a third silicide disposed on the top surface of the third conductive layer.

9. The semiconductor structure of claim 1 , further comprising:
a first spacer above the substrate and contacting to a sidewall surface of the first conductive layer;
a second spacer above the first conductive layer and contacting to a sidewall surface of the second conductive layer; and
a third spacer above the top surface of the third conductive layer and contacting to the second conductive layer.

10. The semiconductor structure of claim 1 , further comprising an etch stop layer covering the substrate, the second surface of the first conductive layer, the second surface of the second conductive layer and the top surface of the third layer.

11. A capacitor structure, comprising:
a substrate having a top surface and a bottom surface opposite to the top surface, the substrate having a first filled trench;
a first polysilicon disposed in the first trench and above the top surface of the substrate, the first polysilicon having a second filled trench;
a second polysilicon disposed in the second filled trench and above the first polysilicon, the second polysilicon having a third filled trench and being electrically isolated from the first polysilicon;
a third polysilicon disposed in the third filled trench, the third polysilicon being electrically isolated from the second polysilicon;
wherein a distance from a top surface of the third polysilicon to the bottom surface of the substrate is less than a distance from a top surface of the second polysilicon to the bottom surface of the substrate.

12. The capacitor structure of claim 11 , wherein the distance from the top surface of the third polysilicon to the bottom surface of the substrate is less than a distance from a top surface of the first polysilicon to the bottom surface of the substrate.

13. The capacitor structure of claim 11 , wherein the distance from the top surface of the third polysilicon to the bottom surface of the substrate is greater than the thickness of the substrate.

14. The capacitor structure of claim 11 , further comprising
a first dielectric layer disposed between the substrate and the first polysilicon;
a second dielectric layer disposed between the first polysilicon and the second polysilicon; and
a third dielectric layer disposed between the second polysilicon and the third polysilicon.

15. The capacitor structure of claim 11 , further comprising:
a first conductive contact electrically connected to a top surface of the first polysilicon;
a second conductive contact electrically connected to the top surface of the second polysilicon; and
a third conductive contact electrically connected to the top surface of the third polysilicon.

16. The capacitor structure of claim 11 , further comprising:
a first silicide disposed on a top surface of the first polysilicon;
a second silicide disposed on the top surface of the second polysilicon; and
a third silicide disposed on the top surface of the third polysilicon.

17. The capacitor structure of claim 11 , further comprising:
a first spacer above the substrate and contacting to a sidewall surface of the first conductive layer;
a second spacer above the first conductive layer and contacting to a sidewall surface of the second conductive layer; and
a third spacer above the top surface of the third conductive layer and contacting to the second conductive layer.

18. A method of manufacturing a semiconductor structure, comprising:
(a) proving a substrate having a top surface;
(b) forming a trench from the top surface of the substrate into the substrate;
(c) disposing a first dielectric layer on a bottom surface and sidewall surfaces of the trench and on the substrate;
(d) disposing a first conductive layer on the first dielectric layer, the first conductive layer having a first surface in the trench and a second surface above the substrate;
(e) disposing a second dielectric layer on the first conductive layer;
(f) disposing a second conductive layer on the second dielectric layer, the second conductive layer having a first surface in the trench and a second surface above the substrate;
(g) disposing a third dielectric layer on the second conductive layer; and
(h) disposing a third conductive layer in the trench and on the third dielectric layer, wherein a top surface of the third conductive layer is lower than a second surface of the second conductive layer.

19. The method of claim 18 , wherein the top surface of the third conductive layer is lower than the second surface of the first conductive layer.

20. The method of claim 18 , wherein the top surface of the third conductive layer is higher than the top surface of the substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Chung-Yen
• Chan Chih-Jen
• Liu Shih-Chang
• Tsai Chia-Shiung

Classifications

• H10P14/414 Primary

  of metal-silicide materials · CPC title

• H01L28/87

  Electricity · mapped topic

• H01L28/75

  Electricity · mapped topic

• H01L21/32053 Primary

  Electricity · mapped topic

• H10D1/714

  having horizontal extensions · CPC title