Self aligned silicon carbide contact formation using protective layer

Patent metadata

Field	Value
Publication number	US-10049879-B2
Application number	US-201715582940-A
Country	US
Kind code	B2
Filing date	May 1, 2017
Priority date	Sep 14, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.

First claim

What is claimed is:

1. A method of forming a contact structure for a semiconductor device, comprising:
providing a silicon-carbide substrate that comprises: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface;
forming a protective layer on the silicon-carbide substrate such that the protective layer covers an exposed upper side of the dielectric layer that is opposite the main surface and such that the protective layer directly contacts a majority of the exposed upper side, and exposes the doped silicon-carbide contact region at the main surface;
depositing a metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region; and
performing a first rapid thermal anneal process,
wherein a thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.

2. The method of claim 1 , wherein selecting the thermal budget of the first rapid thermal anneal process comprises setting a time and temperature of the first rapid thermal anneal process based upon at least one of: a material composition of the protective layer, a thickness of the protective layer, and a material composition of the metal layer.

3. The method of claim 2 , wherein the protective layer is a layer of silicon nitride (SiN), wherein the time and temperature of the first rapid thermal anneal process is set to be less than 800° Celsius for no more than two minutes.

4. The method of claim 3 , wherein the protective layer is approximately 100 nm thick, and wherein the temperature of the first rapid thermal anneal process is set to be approximately 750° Celsius.

5. The method of claim 1 , further comprising:
removing non-silicidized portions of the metal layer after performing the first rapid thermal anneal; and
performing a second rapid thermal anneal process after removing the non-silicidized portions of the metal layer whereby a remaining portion of the metal layer further silicidizes with the doped silicon-carbide contact region.

6. The method of claim 5 , wherein a thermal budget of the second rapid thermal anneal process is greater than a thermal budget of the first rapid thermal anneal process.

7. The method of claim 6 , wherein the thermal budget of the first rapid thermal anneal process is a temperature of 750° Celsius for no more than two minutes and wherein the thermal budget of the second rapid thermal anneal process is a temperature of 1000° Celsius for no more than four minutes.

8. The method of claim 1 , wherein the portion of the metal layer that directly contacts the doped silicon-carbide contact region fully silicidizes with the doped silicon-carbide contact region during the first rapid thermal anneal process.

9. The method of claim 1 , wherein the protective layer completely covers the exposed upper side of the dielectric layer that is opposite the main surface.

10. A method of forming a silicide on a semiconductor substrate, the method comprising:
providing a silicon-carbide substrate that comprises: a doped silicon-carbide contact region directly adjoining a main surface of the substrate;
forming a dielectric layer on the main surface;
forming a protective layer on an exposed upper side of the dielectric layer that is opposite the main surface immediately after forming the dielectric layer forming an opening in the dielectric layer and the protective layer such that the protective layer and the dielectric layer expose the doped silicon-carbide contact region and cover portions of the main surface that are laterally adjacent to the exposed doped silicon-carbide contact region;
forming a metal layer that directly contacts the doped silicon-carbide contact region at the main surface and covers the protective layer; and
performing a first rapid thermal anneal process,
wherein a thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.

11. The method of claim 10 , wherein the dielectric layer surrounds a gate electrode with a lower region of the dielectric layer disposed between the gate electrode and the main surface and an upper region of the dielectric layer disposed over the gate electrode opposite the lower region.

12. The method of claim 10 , wherein selecting the thermal budget of the first rapid thermal anneal process comprises setting a time and temperature of the first rapid thermal anneal process based upon at least one of: a material composition of the protective layer, a thickness of the protective layer, and a material composition of the metal layer.

13. The method of claim 12 , wherein the protective layer is a layer of silicon nitride (SiN), wherein the time and temperature of the first rapid thermal anneal process is selected to be less than 800° Celsius for no more than two minutes.

14. The method of claim 13 , wherein the protective layer is approximately 100 nm thick, and wherein the temperature of the first rapid thermal anneal process is selected to be approximately 750° Celsius.

15. The method of claim 10 , further comprising:
removing non-silicidized portions of the metal layer after performing the first rapid thermal anneal; and
performing a second rapid thermal anneal process after removing the non-silicidized portions of the metal layer whereby a remaining portion of the metal layer further silicidizes with the doped silicon-carbide contact region.

16. The method of claim 15 , wherein a thermal budget of the second rapid thermal anneal process is greater than a thermal budget of the first rapid thermal anneal process.

17. The method of claim 16 , wherein the thermal budget of the first rapid thermal anneal process is a temperature of 750° Celsius for no more than two minutes and wherein the thermal budget of the first rapid thermal anneal process is a temperature of 1000° Celsius for no more than four minutes.

18. The method of claim 10 , wherein the metal layer that directly contacts the doped silicon-carbide contact region fully silicidizes with the doped silicon-carbide contact region during the first rapid thermal anneal process.

19. A method of forming a silicide on a semiconductor substrate, the method comprising:
providing a silicon-carbide substrate that comprises: a doped silicon-carbide contact region directly adjoining a main surface of the substrate;
forming a dielectric layer on the main surface;
forming a protective layer on an exposed upper side of the dielectric layer that is opposite the main surface immediately after forming the dielectric layer;
forming an opening in the dielectric layer and the protective layer such that the protective layer and the dielectric layer expose the doped silicon-carbide contact region and cover portions of the main surface that are laterally adjacent to the exposed doped silicon-carbide contact region;
forming a metal layer that directly contacts the doped silicon-carbide contact region at the main surface and directly contacts the protective layer; and
performing a first rapid thermal anneal process; and
perf

Assignees

• Infineon Technologies Ag

Inventors

• Joshi Ravi Keshav
• Esteve Romain
• Kahn Markus
• Pekoll Kurt
• Steinbrenner Juergen
• Unegg Gerald

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D64/0115 Primary

  to silicon carbide · CPC title

• H01L21/0485 Primary

  Electricity · mapped topic