Semiconductor device

Patent metadata

Field	Value
Publication number	US-10043742-B2
Application number	US-201815897357-A
Country	US
Kind code	B2
Filing date	Feb 15, 2018
Priority date	Aug 24, 2011
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween. The lower electrode (LEL), the dielectric film (DEC), and the upper electrodes (UEL) constitute MIM capacitors (MCA). One of the upper electrodes (UEL) and another upper electrode (UEL) that are adjacent to each other are arranged at an equal distance (D1), without the guard ring being interposed therebetween. The upper electrodes (UEL) positioned on the outermost periphery and the guard ring (GR) positioned outside those upper electrodes UEL are arranged at a distance equal to the distance (D1) from each other.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a main surface;
a plurality of MIM capacitors arranged in a prescribed region on said main surface of the semiconductor substrate;
said plurality of MIM capacitors each including:
a single plate-shaped lower electrode;
a dielectric film in contact with a top surface of said lower electrode and formed in a same single plate-shaped pattern as said lower electrode; and
a plurality of plate-shaped upper electrodes arranged in a matrix form and in contact with a top surface of said dielectric film; and

a guard ring arranged to continuously surround all of the plurality of MIM capacitors without branching,
wherein the plurality of MIM capacitors are arranged spaced apart from each other by a prescribed distance, and
wherein the guard ring is arranged spaced apart from an outermost MIM capacitor by a distance which is the same as the prescribed distance.

2. The semiconductor device according to claim 1 ,
wherein a planar pattern of each of the plurality of MIM capacitors is a square.

3. The semiconductor device according to claim 2 ,
wherein each of said squares has a length of 5 μm to 1000 μm per side.

4. The semiconductor device according to claim 2 ,
wherein in said plurality of MIM capacitors,
at least two MIM capacitors are arranged along a first direction, and
at least two MIM capacitors are arranged along a second direction crossing said first direction.

5. The semiconductor device according to claim 2 ,
wherein said plurality of MIM capacitors are arranged in equal numbers along a first direction and a second direction crossing said first direction.

6. The semiconductor device according to claim 1 ,
wherein a planar pattern of each of said plurality of MIM capacitors is a rectangle.

7. The semiconductor device according to claim 6 ,
wherein said plurality of MIM capacitors are arranged along a first direction with shorter sides opposed to each other, and along a second direction with longer sides opposed to each other, and
wherein said plurality of MIM capacitors are arranged so that the number of said MIM capacitors arranged along said first direction is greater than the number of said MIM capacitors arranged along the second direction.

8. The semiconductor device according to claim 1 ,
wherein the guard ring is formed on the same layer as the upper electrodes.

9. The semiconductor device according to claim 1 ,
wherein the guard ring is formed by a titanium nitride film.

10. The semiconductor device according to claim 1 ,
wherein the guard ring is fixed to a prescribed potential.

11. The semiconductor device according to claim 10 ,
wherein the prescribed potential is ground potential.

Assignees

• Renesas Electronics Corp

Inventors

• Tomita Kazuo
• Yamada Keiichi

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10D84/212

  of only capacitors · CPC title