Semiconductor device

Patent metadata

Field	Value
Publication number	US-9929086-B2
Application number	US-201615270497-A
Country	US
Kind code	B2
Filing date	Sep 20, 2016
Priority date	Aug 24, 2011
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween. The lower electrode (LEL), the dielectric film (DEC), and the upper electrodes (UEL) constitute MIM capacitors (MCA). One of the upper electrodes (UEL) and another upper electrode (UEL) that are adjacent to each other are arranged at an equal distance (D 1 ), without the guard ring being interposed therebetween. The upper electrodes (UEL) positioned on the outermost periphery and the guard ring (GR) positioned outside those upper electrodes UEL are arranged at a distance equal to the distance (D 1 ) from each other.

First claim

The invention claimed is:

1. A semiconductor integrated circuit device comprising:
a semiconductor substrate;
a plurality of MIM capacitors disposed over the semiconductor substrate, each MIM capacitor including a lower electrode, a dielectric film, and an upper electrode; and
a guard ring arranged to continuously surround all of the plurality of MIM capacitors without branching,
wherein the plurality of MIM capacitors are arranged spaced apart from each other by a prescribed distance,
wherein the guard ring is arranged spaced apart from an outermost MIM capacitor by a distance which is the same as the prescribed distance, and
wherein the guard ring is electrically connected to the lower electrode of the outermost MIM capacitor through a metal layer disposed above the guard ring.

2. A semiconductor integrated circuit device according to claim 1 ,
wherein a planar pattern of each of the plurality of MIM capacitors is a square.

3. A semiconductor integrated circuit device according to claim 2 ,
wherein the prescribed potential is ground potential.

4. A semiconductor integrated circuit device according to claim 1 ,
wherein a planar pattern of each of the plurality of MIM capacitors is a rectangle.

5. A semiconductor integrated circuit device according to claim 1 ,
wherein the guard ring is formed on the same layer as the upper electrode.

6. A semiconductor integrated circuit device according to claim 1 ,
wherein the guard ring is formed by a titanium nitride film.

7. A semiconductor integrated circuit device according to claim 1 ,
wherein the prescribed distance is 1.6 μm.

8. A semiconductor integrated circuit device according to claim 1 ,
wherein the guard ring is fixed to a prescribed potential.

Assignees

• Renesas Electronics Corp

Inventors

• Tomita Kazuo
• Yamada Keiichi

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10D84/212

  of only capacitors · CPC title