Package with passivated interconnects

Patent metadata

Field	Value
Publication number	US-10043740-B2
Application number	US-201615208313-A
Country	US
Kind code	B2
Filing date	Jul 12, 2016
Priority date	Jul 12, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.

First claim

The claimed invention is:

1. A semiconductor package, comprising:
a first build-up dielectric layer disposed over at least a portion of a first passivation layer, the first build-up dielectric layer further having a first surface;
a metal trace disposed over at least a first portion of the first surface, the metal trace having a second surface in contact with the first surface, and a third surface opposing the second surface;
a second passivation layer disposed over at least a portion of the first surface and over at least a portion of the third surface, the second passivation layer comprising a different material than the first build-up dielectric layer;
a second build-up dielectric layer disposed over the second passivation layer; and
a via disposed in the second build-up dielectric and in electrical contact with the metal trace.

2. The semiconductor package of claim 1 , further comprising an adhesion layer disposed between a sidewall of the via and the second build-up dielectric layer.

3. The semiconductor package of claim 2 , wherein the second build-up dielectric layer includes a fourth surface and a fifth surface opposing the fourth surface, wherein the fourth surface is in contact with the second passivation layer, and wherein the adhesion layer partially overlies the fifth surface.

4. The semiconductor package of claim 2 , wherein the adhesion layer comprises at least one of: (i) titanium nitride; (ii) tantalum nitride; (iii) titanium; (iv) tantalum; (v) tungsten; (vi) molybdenum; (vii) cobalt; or (viii) nickel.

5. The semiconductor package of claim 1 , wherein the second passivation layer comprises at least one of: (i) silicon nitride; (ii) silicon dioxide; (iii) silicon oxynitride; (iv) silicon carbonitride; (v) silicon carbide; or (vi) porous silicate glass.

6. The semiconductor package of claim 1 , wherein the metal trace is a first metal trace, and the semiconductor package includes a second metal trace, the second metal trace in contact with the via and at least partially overlying the second build-up dielectric-layer.

7. The semiconductor package of claim 1 , further comprising one or more package-to-board interconnects electrically coupled to the via.

8. The semiconductor package of claim 1 , further comprising at least one electrical component disposed over the second build-up dielectric layer.

9. The semiconductor package of claim 1 wherein the semiconductor package includes a third passivation layer, the third passivation layer at least partially overlying the second build-up dielectric layer.

10. The semiconductor package of claim 1 , wherein there is no second passivation layer between the via and the metal trace.

11. A method, comprising:
providing a first build-up dielectric layer disposed over at least a portion of a first passivation layer, the first build-up dielectric layer further having a first surface;
providing metal trace disposed over at least a first portion of the first surface, the metal trace having a second surface in contact with the first surface, and a third surface opposing the second surface;
providing a second passivation layer disposed over at least a portion of the first surface and over at least a portion of the third surface, the second passivation layer comprising a different material than the first build-up dielectric layer;
providing a second build-up dielectric layer over the passivation layer; and
forming a via disposed in the second build-up dielectric layer.

12. The method of claim 11 , wherein the second passivation layer comprises at least one of: (i) silicon nitride; (ii) silicon dioxide; (iii) silicon oxynitride; (iv) silicon carbonitride; (v) silicon carbide; or (vi) porous silicate glass.

13. The method of claim 11 , further comprising forming an adhesion layer disposed between the second build-up dielectric layer and a sidewall of the via.

14. The method of claim 13 , wherein the adhesion layer comprises at least one of: (i) titanium nitride; (ii) tantalum nitride; (iii) titanium; (iv) tantalum; (v) tungsten; (vi) molybdenum; (vii) cobalt; or (viii) nickel.

15. The method of claim 13 , wherein the second build-up dielectric layer includes a fourth surface and a fifth surface opposing the fourth surface, wherein the fourth surface is in contact with the second passivation layer, and wherein the adhesion layer partially overlies the fifth surface.

16. The method of claim 11 , wherein the metal trace is a first metal trace, the method further comprising providing a second metal trace, the second metal trace in contact with the via and at least partially overlying the second build-up dielectric layer.

17. The method of claim 11 , wherein the metal trace is a first metal trace, the method further comprising providing one or more package-to-board interconnects electrically coupled to the via.

18. The method of claim 11 , the method further comprising providing at least one electrical component disposed over the second build-up dielectric layer.

19. The method of claim 11 , wherein there is no second passivation layer between the via and the metal trace.

20. The method of claim 11 , the method further comprising providing a third passivation layer, the third passivation layer at least partially overlying the second build-up dielectric layer.

Assignees

• Boyapati Sri Ranga Sai
• Manepalli Rahul N
• Seneviratne Dilan
• Pietambaram Srinivas V
• Darmawikarta Kristof
• May Robert Alan
• Salama Islam A
• Intel Corp

Inventors

• Boyapati Sri Ranga Sai
• Manepalli Rahul N
• Seneviratne Dilan
• Pietambaram Srinivas V
• Darmawikarta Kristof
• May Robert Alan
• Salama Islam A

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title