Transistor and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10043671-B2
Application number	US-201615097627-A
Country	US
Kind code	B2
Filing date	Apr 13, 2016
Priority date	Apr 16, 2015
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A junction-less transistor structure and fabrication method thereof are provided. The method includes providing a semiconductor substrate; and forming an epitaxial layer having a first surface and a second surface on the semiconductor substrate. The method also includes forming a plurality of trenches in the epitaxial layer from the first surface thereof; and forming a gate dielectric layer on side and bottom surfaces of the plurality of trenches. Further, the method includes forming a gate electrode layer on the gate dielectric layer and in the plurality of trenches; and forming an insulation layer on the gate electrode layer. Further, the method also includes forming a drain electrode layer on the first surface of the epitaxial layer; removing the semiconductor substrate; and forming a source electrode layer on the second surface of the epitaxial layer.

First claim

What is claimed is:

1. A transistor structure, comprising:
an epitaxial layer having a first surface and a second surface;
a gate dielectric layer formed in the epitaxial layer, wherein the gate dielectric layer is formed on side and bottom surfaces of a plurality of trenches that are formed in the epitaxial layer from the first surface thereof;
a gate electrode layer formed on the gate dielectric layer;
an insulation layer formed on the gate electrode layer, wherein a top surface of the insulation layer is coplanar with a top surface of the epitaxial layer; and
a source electrode layer and a drain electrode layer formed on the first surface and the second surface of the epitaxial layer, respectively, wherein the drain electrode layer is formed on the top surface of the epitaxial layer and the top surface of the insulation layer; the epitaxial layer, the source electrode layer and the drain electrode layer have a same doping type, and no PN junction is formed between the source electrode layer and the drain electrode layer through the epitaxial layer.

2. The transistor structure according to claim 1 , wherein the
epitaxial layer further comprises:
a first epitaxial layer with a first doping concentration formed on a semiconductor substrate;
a second epitaxial layer with a second doping concentration formed on the first epitaxial layer; and
a third epitaxial layer with a third doping concentration formed on the second epitaxial layer,
wherein the first doping concentration and the third doping concentration are greater than the second doping concentration.

3. The transistor structure according to claim 2 , wherein:
the first doping concentration is in a range of approximately 1e18 atom/cm 3 -8e19 atom/cm 3 ;
the second doping concentration is in a range of approximately 5e15 atom/cm 3 -8e17 atom/cm 3 ; and
the third doping concentration is in a range of approximately 1e18 atom/cm 3 -8e19 atom/cm 3 .

4. The transistor structure according to claim 2 , wherein:
a thickness of the first epitaxial layer is in a range of approximately 10 nm-50 nm;
a thickness of the second epitaxial layer is in a range of approximately 10 μm-20 μm; and
a thickness of the third epitaxial layer is in a range of approximately 10 nm-50 nm.

5. The transistor structure according to claim 1 , wherein:
the epitaxial layer is made of a wide band-gap material.

6. The transistor structure according to claim 1 , wherein:
the epitaxial layer is made of one of SiC and GaN.

7. The transistor structure according to claim 1 , wherein:
a distance between adjacent trenches is in a range of approximately 1 μm-3 μm.

8. The transistor structure according to claim 1 , wherein:
a depth of the trenches is 1/10-½ of a total thickness of the epitaxial layer.

9. The transistor structure according to claim 1 , wherein:
a work function difference between the gate electrode layer and the epitaxial layer is greater than approximately 1.5 eV.

10. The transistor structure according to claim 1 , wherein:
a thickness of the insulation layer is in a range of approximately 50 nm-500 nm.

11. The transistor structure according to claim 9 , further comprising:
a work function film formed between the gate dielectric layer and the gate electrode layer to adjust the work function difference.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xiao Deyuan

Classifications

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10P14/43 Primary

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H01L29/2003

  Electricity · mapped topic

• H01L29/7828

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic