Content addressable memory cells, memory arrays and methods of forming the same

Patent metadata

Field	Value
Publication number	US-2016104532-A1
Application number	US-201414512552-A
Country	US
Kind code	A1
Filing date	Oct 13, 2014
Priority date	Oct 13, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F 2 and 36F 2 .

First claim

1 . A content addressable memory cell comprising:
a plurality of transistors comprising a minimum feature size F; and a plurality of memory elements coupled to the plurality of transistors, wherein the content addressable memory cell comprises an area of between 18F 2 and 36F 2 .

2 . The content addressable memory cell of claim 1 , wherein each of the transistors comprises a vertically-oriented pillar-shaped transistor.

3 . The content addressable memory cell of claim 1 , wherein each of the transistors comprises a field-effect transistor or a bipolar transistor.

4 . The content addressable memory cell of claim 1 , wherein each of the memory elements comprises a reversible resistance-switching memory element.

5 . The content addressable memory cell of claim 4 , wherein each of the memory elements comprises one or more of a metal oxide, a solid electrolyte, a phase-change material, a magnetic material, and a carbon material.

6 . The content addressable memory cell of claim 4 , wherein each of the memory elements comprises one or more of NiO, Nb 2 O 5 , TiO 2 , HfO 2 , Al 2 O 3 , MgO x , CrO 2 , VO, BN, TaO 2 , Ta 2 O 3 , and AlN.

7 . A content addressable memory array comprising a plurality of content addressable memory cells of claim 1 .

8 . A content addressable memory cell comprising:
five vertically-oriented pillar-shaped transistors; and two reversible resistance-switching memory elements coupled to the five vertically-oriented pillar-shaped transistors.

9 . The content addressable memory cell of claim 8 , wherein each of the five vertically-oriented pillar-shaped transistors comprises a field-effect transistor or a bipolar transistor.

10 . The content addressable memory cell of claim 8 , wherein each of the reversible resistance-switching memory elements comprises one or more of a metal oxide, a solid electrolyte, a phase-change material, a magnetic material, and a carbon material.

11 . The content addressable memory cell of claim 8 , wherein each of the reversible resistance-switching memory elements comprises one or more of NiO, Nb 2 O 5 , TiO 2 , HfO 2 , Al 2 O 3 , MgO x , CrO 2 , VO, BN, TaO 2 , Ta 2 O 3 , and AlN.

12 . A content addressable memory array comprising a plurality of content addressable memory cells of claim 8 .

13 . A content addressable memory cell for use with a bit line, a complementary bit line, a word select line, a read/write line, a search line, a complementary search line, and a match line, the content addressable memory cell comprising:
a first transistor comprising a first terminal coupled to the bit line, a second terminal coupled to the word select line, and a third terminal; a first reversible resistance-switching element comprising a first terminal coupled to the third terminal of the first transistor, and a second terminal coupled to the read/write line; a second transistor comprising a first terminal coupled to the complementary bit line, a second terminal coupled to the word select line, and a third terminal; a second reversible resistance-switching element comprising a first terminal coupled to the third terminal of the second transistor, and a second terminal coupled to the read/write line; a third transistor comprising a first terminal coupled to the search line, a second terminal coupled to the first terminal of the first reversible resistance-switching element and the third terminal of the first transistor, and a third terminal; a fourth transistor comprising a first terminal coupled to the complementary search line, a second terminal coupled to the first terminal of the second reversible resistance-switching element and the third terminal of the second transistor, and a third terminal; and a fifth transistor comprising a first terminal coupled to the match line, a second terminal coupled to the third terminal of the third transistor and the third terminal of the fourth transistor, and a third terminal coupled to GROUND.

14 . The content addressable memory cell of claim 13 , wherein each of the first, second, third, fourth and fifth transistors comprises a vertically-oriented pillar-shaped transistor.

15 . The content addressable memory cell of claim 13 , wherein each of the first, second, third, fourth and fifth transistors comprises a field-effect transistor or a bipolar transistor.

16 . The content addressable memory cell of claim 13 , wherein the first and second reversible resistance-switching elements each comprise one or more of a metal oxide, a solid electrolyte, a phase-change material, a magnetic material, and a carbon material.

17 . The content addressable memory cell of claim 13 , wherein the first and second reversible resistance-switching elements each comprise one or more of NiO, Nb 2 O 5 , TiO 2 , HfO 2 , Al 2 O 3 , MgO x , CrO 2 , VO, BN, TaO 2 , Ta 2 O 3 , and AlN.

18 . A content addressable memory array comprising a plurality of content addressable memory cells of claim 13 .

19 . A method of forming a content addressable memory cell, the method comprising:
providing a plurality of transistors comprising a minimum feature size F; and providing a plurality of memory elements coupled to the plurality of transistors, wherein the content addressable memory cell comprises an area of between 18F 2 and 36F 2 .

20 . The method of claim 19 , wherein each of the transistors comprises a vertically-oriented pillar-shaped transistor.

21 . The method of claim 19 , wherein each of the transistors comprises a field-effect transistor or a bipolar transistor.

22 . The method of claim 19 , wherein each of the memory elements comprises a reversible resistance-switching memory element.

Assignees

• Sandisk 3D Llc

Inventors

• Petti Christopher J

Classifications

• H01L45/145

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L27/2445

  Electricity · mapped topic

• H01L27/2454

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic