Hardware-based translation lookaside buffer (TLB) invalidation

Patent metadata

Field	Value
Publication number	US-10042777-B2
Application number	US-201615084886-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral component interconnect express PCIE) endpoint (EP). A memory management unit (MMU), which is a hardware element, is included in the host system to provide address translation according to at least one TLB. In one aspect, the MMU is configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from the PCIE EP. In another aspect, the PCIE EP is configured to determine that the at least one TLB needs to be invalidated and provide the TLB invalidation command to invalidate the at least one TLB. By implementing hardware-based TLB invalidation in the host system, it is possible to reduce TLB invalidation delay, thus leading to increased data throughput, reduced power consumption, and improved user experience.

First claim

What is claimed is:

1. A host system, comprising:
at least one processor coupled to a system bus;
a memory controller coupled to the system bus and configured to control a memory; and
a memory management unit (MMU) comprising at least one translation lookaside buffer (TLB), the MMU coupled to the system bus and configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from a peripheral component interconnect express (PCIE) endpoint (EP), wherein the PCIE EP is defined in accordance with PCIE base specification revision 3.0.

2. The host system of claim 1 further comprising a PCIE root complex (RC) coupled to the MMU and the PCIE EP, the PCIE RC configured to:
receive the at least one TLB invalidation command from the PCIE EP; and
provide the at least one received TLB invalidation command to the MMU;
wherein the PCIE RC is defined in accordance with PCIE base specification revision 3.0.

3. The host system of claim 1 , wherein the at least one TLB invalidation command is received in at least one PCIE transport layer packet (TLP) prefix, wherein the PCIE TLP is defined in accordance with PCIE base specification revision 3.0.

4. The host system of claim 1 , wherein the at least one TLB invalidation command is received in at least one PCIE transport layer packet (TLP) header.

5. The host system of claim 1 further comprising the PCIE EP.

6. The host system of claim 1 , wherein the PCIE EP is a wireless local area network communication integrated circuit (IC).

7. The host system of claim 1 provided in an integrated circuit (IC).

8. The host system of claim 1 provided in a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc player; a portable digital video player; and an automobile.

9. A method for invalidating at least one translation lookaside buffer (TLB) in a host system, comprising:
receiving at least one TLB invalidation command from a peripheral component interconnect express (PCIE) endpoint (EP), wherein the PCIE EP is defined in accordance with PCIE base specification revision 3.0; and
invalidating the at least one TLB in response to receiving the at least one TLB invalidation command from the PCIE EP.

10. The method of claim 9 comprising receiving the at least one TLB invalidation command by a PCIE root complex (RC) coupled to the PCIE EP, wherein the PCIE RC is defined in accordance with PCIE base specification revision 3.0.

11. The method of claim 9 comprising receiving the at least one TLB invalidation command in at least one PCIE transport layer packet (TLP) prefix, wherein the PCIE TLP is defined in accordance with PCIE base specification revision 3.0.

12. The method of claim 9 comprising receiving the at least one TLB invalidation command in at least one PCIE transport layer packet (TLP) header.

13. A peripheral component interconnect express (PCIE) endpoint (EP) defined in accordance with PCIE base specification revision 3.0, comprising:
a host interface controller (HIC) communicatively coupled to a host system, wherein the HIC is configured to:
determine that at least one translation lookaside buffer (TLB) in the host system needs to be invalidated; and
provide at least one TLB invalidation command to the host system to invalidate the at least one TLB.

14. The PCIE EP of claim 13 , wherein the HIC is communicatively coupled to the host system by a PCIE root complex (RC) in the host system, wherein the PCIE RC is defined in accordance with PCIE base specification revision 3.0.

15. The PCIE EP of claim 13 , wherein the HIC is configured to provide the at least one TLB invalidation command in at least one PCIE transport layer packet (TLP) prefix, wherein the PCIE TLP is defined in accordance with PCIE base specification revision 3.0.

16. The PCIE EP of claim 13 , wherein the HIC is configured to provide the at least one TLB invalidation command in at least one PCIE transport layer packet (TLP) header.

17. The PCIE EP of claim 13 is comprised of a wireless local area network communication integrated circuit (IC).

18. A method for invalidating at least one translation lookaside buffer (TLB) in a host system, comprising:
communicatively coupling a host interface controller (HIC) in a peripheral component interconnect express (PCIE) endpoint (EP) to a host system;
determining by the HIC at least one TLB in the host system that needs to be invalidated based on detected data patterns of one or more data blocks; and
providing at least one TLB invalidation command from the HIC to the host system to invalidate the at least one TLB.

19. The method of claim 18 comprising providing the at least one TLB invalidation command in at least one peripheral component interconnect express (PCIE) transport layer packet (TLP) prefix, wherein the PCIE TLP is defined in accordance with PCIE base specification revision 3.0.

20. The method of claim 18 comprising providing the at least one TLB invalidation command in at least one PCIE transport layer packet (TLP) header.

Assignees

• Qualcomm Inc

Inventors

• Shacham Assaf
• Yifrach Shaul Yohai
• Zeng Thomas

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title