Invalidating stored address translations

Patent metadata

Field	Value
Publication number	US-2015242319-A1
Application number	US-201414186091-A
Country	US
Kind code	A1
Filing date	Feb 21, 2014
Priority date	Feb 21, 2014
Publication date	Aug 27, 2015
Grant date	—

Abstract

A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.

First claim

We claim:

1 . Apparatus for data processing, comprising:
data processing circuitry configured to perform data processing operations with reference to data values stored in a memory, wherein each data processing operation has an identifier associated therewith; and address translation circuitry configured to store address translations between first addresses used in a first addressing system corresponding to the data processing operations performed by the data processing circuitry and second addresses used in a second addressing system used by the memory, wherein each stored address translation is stored with a corresponding identifier, wherein the address translation circuitry is configured to respond to an invalidation command to perform an invalidation process on a selected stored address translation to invalidate the selected stored address translation, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier, and the address translation circuitry is further configured to perform the invalidation process further configured by identifier grouping information, wherein the identifier grouping information associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.

2 . The apparatus as claimed in claim 1 , wherein the data processing circuitry is configured to host a plurality of virtual machines to perform the data processing operations and the corresponding identifier stored by the address translation circuitry in association with each address translation is a virtual machine identifier.

3 . The apparatus as claimed in claim 1 , wherein the address translation circuitry is configured to store the identifier grouping information in association with each stored address translation.

4 . The apparatus as claimed in claim 3 , wherein the identifier grouping information specifies a portion of the specified identifier in the invalidation command which is to be ignored when matching stored address translations for the invalidation process.

5 . The apparatus as claimed in claim 4 , wherein the identifier grouping information specifies whether the portion of the specified identifier is a most significant portion or a least significant portion.

6 . The apparatus as claimed in claim 3 , wherein the identifier grouping information is configurable to specify a no broadcast marker, such that the invalidation process is not performed for a stored address translation marked with the no broadcast marker in response to the invalidation command if the invalidation command is received as a broadcast invalidation command.

7 . The apparatus as claimed in claim 1 , wherein the apparatus is configured to store the identifier grouping information accessible to the address translation circuitry for application to all address invalidation processes performed by the address translation circuitry.

8 . The apparatus as claimed in claim 1 , wherein the address translation circuitry is configured to identify the identifier grouping information within the invalidation command.

9 . The apparatus as claimed in claim 8 , wherein the data processing circuitry is configured to operate in one of two data processing modes, wherein in a first data processing mode the data processing circuitry is configured to issue the invalidation command without the identifier grouping information and the apparatus is configured to add the identifier grouping information to the invalidation command, and wherein in a second data processing mode the data processing circuitry is configured to issue the invalidation command and to add the identifier grouping information to the invalidation command itself.

10 . The apparatus as claimed in claim 1 , wherein the data processing circuitry comprises at least two data processing devices, wherein for each group of identifiers the address translation circuitry is configured to provide address translations for a first data processing device of the at least two data processing devices for only a first identifier of that group of identifiers and to provide an address translation for a second data processing device of the at least two data processing devices for any identifier of that group of identifiers.

11 . The apparatus as claimed in claim 1 , wherein the address translation circuitry is configured to perform a lookup process to determine if an address translation is stored for a received first address and a received identifier, and the address translation circuitry is configured to store a lookup match modifier in association with each stored address translation, and wherein when the lookup match modifier has a first value the lookup process is configured only to find the address translation if the received identifier fully matches a stored identifier, and when the lookup match modifier has a second value the lookup process is configured to find the address translation if the received identifier matches any identifier in a group of identifiers to which the stored identifier belongs as defined by identifier grouping information for the stored identifier.

12 . The apparatus as claimed in claim 11 , wherein the address translation circuitry is configured, if no address translation is found as a result of the lookup process, to initiate a retrieval process to fetch the address translation from memory, and, if the lookup match modifier has the first value and the retrieval process shows that no address translation was found as the result of the lookup process because the received identifier did not match but the received identifier belongs to a group of identifiers to which a stored identifier in the address translation circuitry which does match also belongs, and the retrieval process shows that the address translation fetched from memory otherwise matches the address translation stored for the stored identifier, the address translation circuitry is further configured to change the lookup match modifier for the stored identifier to have the second value.

13 . The apparatus as claimed in claim 1 , wherein the address translation circuitry is a translation lookaside buffer configured to store address translations for page tables in the first addressing system to page tables in the second addressing system.

14 . The apparatus as claimed in claim 1 , wherein the data processing circuitry comprises at least two data processing devices, wherein a first data processing device of the at least two data processing devices is a general purpose central processing unit and a second data processing device of the at least two data processing devices is a slave device configured to perform at least some of the data processing operations on behalf of the general purpose central processing unit.

15 . A method of data processing comprising the steps of:
performing data processing operations with reference to data values stored in a memory, wherein each data processing operation has an identifier associated therewith; storing address translations between first addresses used in a first addressing system corresponding to the data processing operations performed by the data processing circuitry and second addresses used in a second addressing system used by the memory, wherein each stored address translation is stored with a corresponding identifier; performing an invalidation process in response to an invalidation command on a selec

Assignees

• Advanced Risc Mach Ltd

Inventors

• Evans Matthew L
• Persson Hakan Lars-Goran
• Parker Jason
• Stockwell Gareth
• Rose Andrew Christopher

Classifications

• G06F12/109 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title