Access log and address translation log for a processor

Patent metadata

Field	Value
Publication number	US-2016378682-A1
Application number	US-201514747980-A
Country	US
Kind code	A1
Filing date	Jun 23, 2015
Priority date	Jun 23, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

First claim

What is claimed is:

1 . A method comprising:
recording, at a processor, a first log indicating a set of physical memory addresses associated with a stream of cache misses at the processor; and providing the first log to software executing at the processor.

2 . The method of claim 1 , further comprising:
recording, at the processor, a second log indicating a mapping of the set of physical memory addresses to a corresponding set of virtual addresses; and providing the second log to the software executing at the processor.

3 . The method of claim 2 , wherein providing the first log and the second log comprises:
providing the first log and the second log to the software in response to a number of physical memory addresses in the first set exceeding a threshold.

4 . The method of claim 2 , wherein the first log comprises a plurality of entries, each entry comprising:
a first field indicating a physical address associated with memory access request that resulted in a cache miss at the processor; and a second field indicating a type of the memory access request.

5 . The method of claim 2 , further comprising:
in response to an indication of a flush at a translation lookaside buffer (TLB) of the processor, recording the TLB flush at the second log.

6 . The method of claim 5 , further comprising:
marking an entry of the log as invalid in response to a request; and omitting the marked entry from the second log in response to recording the TLB flush.

7 . The method of claim 2 , further comprising:
in response to a memory access request resulting in a cache miss, omitting a physical address of the memory access request from the first log in response to determining the physical address is located in an excluded region of memory.

8 . The method of claim 7 , further comprising:
determining the physical address is located in the excluded region of memory based on an entry of a page table including the physical address.

9 . The method of claim 2 , wherein providing the first log comprises:
filtering a physical address from the first log in response to determining the physical address is located in an excluded region of memory.

10 . A method, comprising:
periodically sampling, at a processor, a set of physical memory addresses associated with a stream of cache misses at the processor to generate a first log; recording, at the processor, a second log indicating a mapping of the set of physical memory addresses to a corresponding set of virtual addresses; and providing the first log and the second log to software executing at the processor.

11 . The method of claim 10 , wherein recording the second log comprises:
recording a mapping of a physical address to a corresponding virtual address at the second log in response to a page table walk to identify the physical address.

12 . The method of claim 10 , wherein providing the first log and the second log comprises:
providing the first log and the second log to the software in response to a number of physical memory addresses in the first set exceeding a threshold.

13 . A processor comprising:
a processor core to execute software; a cache; and a stream recording module to record a first log indicating a set of physical memory addresses associated with a stream of cache misses at the cache and to provide the first log to the software.

14 . The processor of claim 13 , further comprising
an address recording module to record a second log indicating a mapping of the set of physical memory addresses to a corresponding set of virtual addresses and to provide the second log to the software.

15 . The processor of claim 14 , wherein the stream recording module is to provide the first log to the software in response to a number of physical memory addresses in the first set exceeding a threshold.

16 . The processor of claim 14 , wherein the first log comprises a plurality of entries, each entry comprising:
a first field indicating a physical address associated with memory access request that resulted in a cache miss at the processor; and a second field indicating a type of the memory access request.

17 . The processor of claim 16 , further comprising:
a translation lookaside buffer (TLB); and wherein the address recording module, is to record a TLB flush at the second log, in response to an indication of a flush at the TLB.

18 . The processor of claim 16 , wherein:
the stream recording module is to omit a physical address of the memory access request from the first log in response to determining the physical address is located in an excluded region of memory.

19 . The processor of claim 18 , wherein:
the stream recording module is to identify that the physical address is located in the excluded region of memory based on an entry of a page table including the physical address.

20 . The processor of claim 14 , wherein:
in response to the software receiving the first log and the second log, the processor is to transfer a block of data associated with the set of physical to a cache of the processor.

Assignees

• Avanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Sander Benjamin T
• Fowler Mark
• Asaro Anthony
• Cheng Gongxian Jeffrey
• Mantor Mike

Classifications

• G06F2212/684

  TLB miss handling · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/0893

  Caches characterised by their organisation or structure · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F2212/69

  Physics · mapped topic