Semiconductor device and transistor cell having a diode region

Patent metadata

Field	Value
Publication number	US-10038087-B2
Application number	US-201715858730-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	May 23, 2014
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

According to an embodiment of a semiconductor device, the device includes a semiconductor body with a drift region and neighboring device cells integrated in the semiconductor body. Each device cell includes: a body region arranged between a source region and the drift region; a diode region and a pn junction between the diode region and the drift region; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; and a gate electrode arranged in the trench and dielectrically insulated from the semiconductor body by a gate dielectric. The diode regions together with the drift region act as a JFET, which has a channel region in the drift region between the diode regions. The drift region has a locally increased doping concentration in the channel region of the JFET.

First claim

What is claimed is:

1. A semiconductor device, comprising a semiconductor body and at least one device cell integrated in the semiconductor body, the at least one device cell comprising:
a drift region, a source region, and a body region arranged between the source region and the drift region;
a diode region and a pn junction between the diode region and the drift region;
a trench with a first sidewall, a second sidewall opposite the first sidewall, and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom of the trench; and
a gate electrode arranged in the trench and dielectrically insulated from the semiconductor body by a gate dielectric,
wherein the diode region extends below the bottom of the trench,
wherein the drift region has a locally increased doping concentration in a region between a pn junction at the border between the body region and the drift region and a lower end of the diode region.

2. The semiconductor device of claim 1 , wherein the gate dielectric has a first thickness at the first sidewall of the trench and a second thickness at the second sidewall of the trench, and wherein the second thickness is greater than the first thickness.

3. The semiconductor device of claim 1 , wherein the gate dielectric has a first thickness at the first sidewall of the trench and a third thickness at the bottom of the trench, and wherein the third thickness is greater than the first thickness.

4. The semiconductor device of claim 1 , wherein the trench has a rounded corner between the first sidewall and the bottom, and wherein a radius of the rounded corner is at least 2 times a thickness of the gate dielectric at the first sidewall.

5. The semiconductor device of claim 1 , further comprising:
a source electrode electrically connected to the source region and the diode region of each device cell.

6. The semiconductor device of claim 5 , wherein the diode region comprises:
a first diode region forming the pn-junction with the drift region; and
a second diode region more highly doped than the first diode region and connected to the source electrode.

7. The semiconductor device of claim 6 , wherein the second diode region adjoins the second sidewall of the trench.

8. The semiconductor device of claim 6 , wherein the first diode region has a maximum doping concentration distant to the bottom of the trench.

9. The semiconductor device of claim 8 , wherein the first diode region has a local minimum of the doping concentration between a position of the maximum doping concentration and the bottom of the trench.

10. The semiconductor device of claim 1 , wherein the semiconductor body comprises a SiC crystal, and wherein the first sidewall of the trench is aligned with a c-axis of the SiC crystal.

11. The semiconductor device of claim 10 , wherein an angle between the first surface of the semiconductor body and the first sidewall of the trench is between 80° and 89°.

12. The semiconductor device of claim 1 , wherein the region of the drift region with the locally increased doping concentration has a thickness in a range between 200 nanometers and 1 micrometer.

13. The semiconductor device of claim 1 , wherein the region of the drift region with the locally increased doping concentration has a doping concentration of at least 2 times greater than the doping concentration of the drift region outside the region with the locally increased doping concentration.

14. The semiconductor device of claim 1 , wherein the doping concentration of the region of the drift region with the locally increased doping concentration is in a range between 5E16 cm −3 and 1E17 cm −3 , and wherein the doping concentration of the drift region outside the region with the locally increased doping concentration is below 2E16 cm −3 .

15. A semiconductor device, comprising:
a semiconductor body with a drift region; and
neighboring device cells integrated in the semiconductor body,
wherein the neighboring device cells each comprise:
a source region;
a body region arranged between the source region and the drift region;
a diode region and a pn junction between the diode region and the drift region;
a trench with a first sidewall, a second sidewall opposite the first sidewall, and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom of the trench; and
a gate electrode arranged in the trench and dielectrically insulated from the semiconductor body by a gate dielectric,

wherein the diode regions of the neighboring device cells together with the drift region act as a JFET (Junction Field-Effect Transistor),
wherein a region of the drift region between the diode regions of the neighboring device cells forms a channel region of the JFET,
wherein the drift region has a locally increased doping concentration in the channel region of the JFET.

16. The semiconductor device of claim 15 , wherein the channel region of the JFET extends from a pn junction at the border between the body regions of the neighboring device cells and the drift region to a vertical position of a lower end of the diode regions of the neighboring device cells.

17. The semiconductor device of claim 15 , wherein the channel region of the JFET has a thickness in a range between 200 nanometers and 1 micrometer.

18. The semiconductor device of claim 15 , wherein the channel region of the JFET has a doping concentration of at least 2 times greater than the doping concentration of the drift region outside the channel region.

19. The semiconductor device of claim 15 , wherein the channel region of the JFET has a doping concentration in a range between 5E16 cm −3 and 1E17 cm −3 , and wherein the doping concentration of the drift region outside the channel region of the JFET is below 2E16 cm −3 .

20. The semiconductor device of claim 15 , wherein the diode region of each neighboring device cell comprises:
a first diode region forming the pn-junction with the drift region; and
a second diode region more highly doped than the first diode region and connected to a source electrode.

Assignees

• Infineon Technologies Ag

Inventors

• Siemieniec Ralf
• Bergner Wolfgang
• Esteve Romain
• Peters Dethard

Classifications

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title