Semiconductor device having super junction metal oxide semiconductor structure and fabrication method for the same

Patent metadata

Field	Value
Publication number	US-2016284835-A1
Application number	US-201615173652-A
Country	US
Kind code	A1
Filing date	Jun 4, 2016
Priority date	Sep 1, 2008
Publication date	Sep 29, 2016
Grant date	—

Abstract

A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

First claim

1 . A semiconductor device comprising:
a first base layer of a first conductivity type; a drain layer of the first conductivity type formed on a back side surface of the first base layer; a second base layer of a second conductivity type formed in a surface side of the first base layer; a source layer of the first conductivity type formed in a surface side of the second base layer; a gate insulating film disposed on a surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer of the second conductivity type formed in the first base layer directly below both the second base layer and the source layer by opposing the drain layer so that a long-side direction of the column layer is a direction vertical to a principal surface of the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein the column layer and the first base layer are alternately-arranged repeatedly in a direction parallel to the principal surface of the drain layer, and a bottom surface of the column layer and a top surface of the drain layer are separated from each other, wherein the column layer is subjected to a charged particle irradiation of which particle species is one of 3 He ++ and 4 He ++ , and thereby a trap level was locally formed so that a peak position where an impurity concentration of the first conductivity type becomes the lowest is included between the bottom surface of the column layer and the top surface of the drain layer.

2 . The semiconductor device according to claim 1 , wherein the charged particle irradiation is subjected to a lower part of the column layer to form the trap level locally.

3 . The semiconductor device according to claim 2 , wherein the trap level is due to the charged particle irradiation.

4 . The semiconductor device according to claim 1 , wherein the attenuation peak position of the charged particle irradiation is included between: a first position between the bottom surface of the column layer and the top surface of the drain layer; and a second position between the bottom surface of the column layer and the top surface of the drain layer, the first position determined by obtaining a distance from the bottom surface of the column layer so that reverse recovery time is shorter than a predetermined time period, the second position determined by obtaining a distance from the bottom surface of the column layer so that a saturation current between the drain and the sources is lower than a predetermined saturation current, on the basis of the bottom surface of the column layer.

5 . The semiconductor device according to claim 1 , wherein an amount of dosage of the charged particle irradiation is 5×10 10 /cm 2 to 5×10 12 /cm 2 .

6 . The semiconductor device according to claim 1 , wherein a planar pattern on the basis of one of a rectangle and a hexagon is disposed being checkered lattice-like or zigzagged checkered lattice-like, in the first base layer, the second base layer, and the source layer.

7 . The semiconductor device according to claim 1 , wherein the bottom surface of the column layer and the drain layer are separated by the first base layer.

8 . The semiconductor device according to claim 1 , wherein the trap level extends over the column layer and the first base layer.

9 . The semiconductor device according to claim 1 , wherein a distance between two neighboring column layers is smaller than a width of each of the column layers.

10 . A fabrication method for a semiconductor device, the fabrication method comprising:
forming a first base layer of a first conductivity type; forming a drain layer of the first conductivity type on a back side surface of the first base layer; forming a second base layer of a second conductivity type in a surface side in the first base layer; forming a source layer of the first conductivity type in a surface side in the second base layer; forming a gate insulating film on a surface of both the source layer and the second base layer; forming a gate electrode on the gate insulating film; forming a column layer of the second conductivity type in the first base layer directly below both the second base layer and the source layer by opposing the drain layer so that a long-side direction of the column layer is a direction vertical to a principal surface of the drain layer; forming a drain electrode in the drain layer, forming a source electrode on both the source layer and the second base layer; and performing a charged particle irradiation of which particle species is one of 3 He ++ and 4 He ++ with respect to the column layer, and thereby forming a trap level was locally so that a peak position where an impurity concentration of the first conductivity type becomes the lowest is included between the bottom surface of the column layer and the top surface of the drain layer, wherein the column layer and the first base layer are alternately-arranged repeatedly in a direction parallel to the principal surface of the drain layer, and a bottom surface of the column layer and a top surface of the drain layer are separated from each other.

11 . The fabrication method for the semiconductor device according to claim 10 , wherein the charged particle irradiation is performed to a lower part of the column layer to form the trap level locally.

12 . The fabrication method for the semiconductor device according to claim 11 , wherein the trap level is due to the charged particle irradiation.

13 . The fabrication method for the semiconductor device according to claim 10 , wherein the step of forming the trap level locally includes:
determining a first position between the bottom surface of the column layer and the top surface of the drain layer, the first position determined by obtaining a distance from the bottom surface of the column layer so that reverse recovery time is shorter than a predetermined time period, on the basis of the bottom surface of the column layer; determining a second position between the bottom surface of the column layer and the top surface of the drain layer, the second position determined by obtaining a distance from the bottom surface of the column layer so that a saturation current between the drain and the sources is lower than a predetermined saturation current; and performing the charged particle irradiation so that an attenuation peak position is included between the first position and the second position.

14 . The fabrication method for the semiconductor device according to claim 10 , wherein an amount of dosage of the charged particle irradiation is 5×10 10 /cm 2 to 5×10 12 /cm 2 .

15 . The fabrication method for the semiconductor device according to claim 10 , wherein a planar pattern on the basis of one of a rectangle and a hexagon is disposed being checkered lattice-like or zigzagged checkered lattice-like, in the first base layer, the second base layer, and the source layer.

16 . The fabrication method for the semiconductor device according to claim 10 , wherein the trap level is formed both along the first direction and along a second direction parallel to the principal surface of the drain layer so as to contact both of the column layer and the first base layer.

Assignees

• Rohm Co Ltd

Inventors

• Nakajima Toshio

Classifications

• H10P34/40

  with high-energy radiation · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D84/144

  in antiparallel diode configurations · CPC title