UV and reducing treatment for K recovery and surface clean in semiconductor processing

US10037905B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10037905-B2
Application numberUS-64683009-A
CountryUS
Kind codeB2
Filing dateDec 23, 2009
Priority dateNov 12, 2009
Publication dateJul 31, 2018
Grant dateJul 31, 2018

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor device, comprising: receiving in a processing chamber a semiconductor device substrate comprising conductive features and a dielectric layer having formed therein a feature; and exposing the semiconductor device substrate to a reducing agent and UV radiation, without exposing the device substrate to a plasma, wherein the reducing agent is a reducing gas selected from the group consisting of NH 3 , NH 2 D, NHD 2 , ND 3 , H 2 , N 2 H 4 , and combinations of these with one another and/or inert gases, such that oxide on the conductive features is removed in a UV-mediated plasma-free process including exposure to a non-oxidizing reducing environment, wherein the UV and reducing agent exposure reduces oxide created in a via silicide. 2. A method of forming a semiconductor device, comprising: receiving in a processing chamber a semiconductor device substrate comprising conductive features and a dielectric layer having formed therein a feature; and exposing the semiconductor device substrate to a reducing agent and UV radiation, without exposing the device substrate to a plasma, wherein the reducing agent is a reducing gas selected from the group consisting of NH 3 , NH 2 D, NHD 2 , ND 3 , H 2 , N 2 H 4 , and combinations of these with one another and/or inert gases, such that oxide on the conductive features is removed in a UV-mediated plasma-free process including exposure to a non-oxidizing reducing environment, and wherein the reducing agent is NH 3 gas, the exposure to the reducing agent is conducted at a temperature of about 400° C. for less than 1 minute, and the UV radiation exposure is conducted in an inert atmosphere. 3. A method of forming a semiconductor device, comprising: receiving in a processing chamber a semiconductor device substrate comprising conductive features and a dielectric layer having formed therein a feature; and exposing the semiconductor device substrate to a reducing agent and UV radiation, without exposing the device substrate to a plasma, wherein the reducing agent is a reducing gas selected from the group consisting of NH 3 , NH 2 D, NHD 2 , ND 3 , H 2 , N 2 H 4 , and combinations of these with one another and/or inert gases, such that oxide on the conductive features is removed in a UV-mediated plasma-free process including exposure to a non-oxidizing reducing environment, and wherein the reducing gas is selected from the group consisting of NH 2 D, NHD 2 and ND 3 . 4. A method of forming a semiconductor device, comprising: receiving in a processing chamber a semiconductor device substrate comprising conductive features and a dielectric layer having formed therein a feature; and exposing the semiconductor device substrate to a reducing agent and UV radiation, without exposing the device substrate to a plasma, wherein the reducing agent is a reducing gas selected from the group consisting of NH 3 , NH 2 D, NHD 2 , ND 3 , H 2 , N 2 H 4 , and combinations of these with one another and/or inert gases, such that oxide on the conductive features is removed in a UV-mediated plasma-free process including exposure to a non-oxidizing reducing environment, and wherein the UV-mediated plasma-free process comprises exposing the oxide to hydrogen radicals. 5. A method of forming a semiconductor device, comprising: receiving in a processing chamber a semiconductor device substrate comprising a planarized surface having conductive features in a dielectric layer; and exposing the planarized surface to UV radiation and a reducing agent, without exposing the planarized surface to a plasma, wherein the reducing agent is a reducing gas selected from the group consisting of NH 3 , NH 2 D, NHD 2 , ND 3 , H 2 , N 2 H 4 ,and combinations of these with one another and/or inert gases; whereby oxide on the conductive features is removed in a UV-mediated plasma-free process including exposure to a non-oxidizing reducing environment, wherein the UV-mediated plasma-free process comprises exposing the oxide to hydrogen radicals.

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Inventors

Classifications

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • the processing being a planarisation of conductive layers · CPC title

  • the processing being the formation of vias or contact holes · CPC title

  • by contacting with gases, liquids or plasmas · CPC title

  • by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

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What does patent US10037905B2 cover?
Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. T…
Who is the assignee on this patent?
Varadarajan Bhadri, Antonelli George A, Van Schravendijk Bart, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10P72/0436. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 31 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).