Method for implanting ions into a semiconductor substrate and an implantation system

Patent metadata

Field	Value
Publication number	US-10037887-B2
Application number	US-201715435034-A
Country	US
Kind code	B2
Filing date	Feb 16, 2017
Priority date	Feb 18, 2016
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A method for implanting ions into a semiconductor substrate includes performing a test implantation of ions into a semiconductor substrate. The ions of the test implantation are implanted with a first implantation angle range over the semiconductor substrate. Further, the method includes determining an implantation angle offset based on the semiconductor substrate after the test implantation and adjusting a tilt angle of the semiconductor substrate with respect to an implantation direction based on the determined implantation angle offset. Additionally, the method includes performing at least one target implantation of ions into the semiconductor substrate after the adjustment of the tilt angle. The ions of the at least one target implantation are implanted with a second implantation angle range over the semiconductor substrate. Further, the first implantation angle range is larger than the second implantation angle range.

First claim

What is claimed is:

1. A method for implanting ions into a semiconductor substrate, the method comprising:
performing a test implantation of ions into the semiconductor substrate, wherein the ions of the test implantation are implanted with a first implantation angle range over the semiconductor substrate;
determining an implantation angle offset based on the semiconductor substrate after the test implantation;
adjusting a tilt angle of the semiconductor substrate with respect to an implantation direction based on the determined implantation angle offset; and
performing at least one target implantation of ions into the semiconductor substrate after the adjustment of the tilt angle, wherein the ions of the at least one target implantation are implanted with a second implantation angle range over the semiconductor substrate, wherein the first implantation angle range is larger than the second implantation angle range.

2. The method according to claim 1 , wherein the first implantation angle range is larger than 0.8°.

3. The method according to claim 1 , wherein the second implantation angle range is lower than 0.5°.

4. The method according to claim 1 , wherein performing the test implantation comprises moving the semiconductor substrate through an ion beam of the test implantation while a tilt angle of the semiconductor substrate is varied.

5. The method according to claim 1 , wherein an ion beam divergence during the test implantation is larger than an ion beam divergence during the at least one target implantation.

6. The method according to claim 5 , wherein beam divergence correction measures are reduced during the test implantation with respect to the at least one target implantation.

7. The method according to claim 1 , wherein determining the implantation angle offset comprises measuring a crystal defect density or charge carrier density of at least a plurality of laterally different positions at the semiconductor substrate to obtain a lateral crystal defect density distribution or a lateral charge carrier density distribution.

8. The method according to claim 7 , wherein the crystal defect density or charge carrier density distribution is measured by a laser-based measurement method or a Rutherford Backscattering Spectrometry method.

9. The method according to claim 1 , wherein determining the implantation angle offset comprises determining a position at the semiconductor substrate at which channeling conditions occurred during the test implantation.

10. The method according to claim 1 , wherein the tilt angle is adjusted so that channeling conditions are obtained for the at least one target implantation.

11. The method according to claim 1 , wherein the test implantation and the at least one target implantation are performed by the same ion implantation module.

12. The method according to claim 1 , wherein the test implantation is performed at an implantation energy of less than 50 keV.

13. The method according to claim 1 , wherein the test implantation is performed at an implantation dose of less than 3×1012 cm−2.

14. The method according to claim 1 , wherein the ions of the test implantation are protons.

15. The method according to claim 1 , wherein the doping of at least one of the group comprising a portion of a compensation region of a superjunction device, a body region of a transistor, a field stop region, a back side emitter region, a junction termination extension structure, a channel stopper region, a buried back side doping region, a drift region and a field stop/emitter-shorting region is implanted by the at least one target implantation.

16. The method according to claim 1 , further comprising determining a twist angle of the semiconductor substrate based on the semiconductor substrate after the test implantation.

Assignees

• Infineon Technologies Ag

Inventors

• Brugger Michael
• Jelinek Moriz
• Laven Johannes Georg
• Schulze Hans-Joachim
• Schustereder Werner

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P30/222 Primary

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P72/04

  Apparatus for manufacture or treatment · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title