Infrared focal plane readout integrated circuit

Patent metadata

Field	Value
Publication number	US-10036669-B1
Application number	US-201715712287-A
Country	US
Kind code	B1
Filing date	Sep 22, 2017
Priority date	Aug 15, 2017
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

An infrared focal plane readout integrated circuit that includes a unit bias circuit, an integrating circuit, and an on-chip analog-to-digital conversion circuit, where the integrating circuit includes a first switch tube, a second switch tube, and an integrating capacitor; an output end of the unit bias circuit is connected to an input end of the first switch tube; an input end of the second switch tube is connected to a set terminal; both an output end of the first switch tube and an output end of the second switch tube are connected to one end of an integrating capacitor and an input end of the on-chip analog-to-digital conversion circuit; the other end of the integrating capacitor is grounded; and the on-chip analog-to-digital conversion circuit includes a first inverter, a second inverter, a third inverter, an exclusive-OR gate, a built-in sequence counter, and a register.

First claim

What is claimed is:

1. An infrared focal plane readout integrated circuit, comprising:
a unit bias circuit, an integrating circuit, and an on-chip analog-to-digital conversion circuit, wherein the integrating circuit comprises a first switch tube, a second switch tube, and an integrating capacitor; and
an output end of the unit bias circuit is connected to an input end of the first switch tube, an input end of the second switch tube is connected to a set terminal of the integrating circuit, an output end of the first switch tube and an output end of the second switch tube are separately connected to one end of the integrating capacitor, the other end of the integrating capacitor is grounded, and an input end of the on-chip analog-to-digital conversion circuit is separately connected to the output end of the first switch tube and the output end of the second switch tube.

2. The infrared focal plane readout integrated circuit according to claim 1 , wherein the on-chip analog-to-digital conversion circuit comprises a comparison circuit, a built-in sequence counter, and a register, wherein an input end of the comparison circuit is connected to an output end of the integrating circuit; the comparison circuit comprises two output ends, one output end is connected to a data end of the register, and the other end is connected to an enable end of the register; and an output end of the built-in sequence counter is connected to the data end of the register.

3. The infrared focal plane readout integrated circuit according to claim 2 , wherein the comparison circuit comprises a first inverter, a second inverter, a third inverter, and an exclusive-OR gate, wherein input ends of the first inverter and the second inverter are separately connected to the output end of the integrating circuit; an output end of the first inverter is separately connected to an input end of the third inverter and an input end of the exclusive-OR gate; an output end of the second inverter is connected to another input end of the exclusive-OR gate; an output end of the third inverter is connected to the data end of the register; and an output end of the exclusive-OR gate is connected to the enable end of the register.

4. The infrared focal plane readout integrated circuit according to claim 1 , wherein the unit bias circuit comprises a first resistor, a second resistor, a first transistor, and a second transistor, wherein one end of the first resistor is connected to a first bias signal end, and the other end is connected to a source terminal of the first transistor; a drain terminal of the first transistor is connected to a drain terminal of the second transistor; a source terminal of the second transistor is connected to one end of the second resistor; the other end of the second resistor is grounded; a grid terminal of the first transistor is connected to a second bias signal end; a grid terminal of the second transistor is connected to a third bias signal end; and both the drain terminal of the first transistor and the drain terminal of the second transistor are connected to an input end of the integrating circuit.

5. The infrared focal plane readout integrated circuit according to claim 2 , wherein the built-in sequence counter is an inverted sequence counter.

6. The infrared focal plane readout integrated circuit according to claim 3 , wherein a turnover voltage of the first inverter is greater than a reference voltage of the set terminal, and the reference voltage is greater than a turnover voltage of the second inverter.

7. The infrared focal plane readout integrated circuit according to claim 1 , wherein the register comprises multiple D triggers.

Assignees

• Univ Electronic Sci & Tech China

Inventors

• Lv Jian
• Que longcheng
• Qin Jinyu
• Wan Yue
• Wang Qiming
• Jiang Yadong

Classifications

• G01J5/24 Primary

  Use of specially adapted circuits, e.g. bridge circuits · CPC title

• G01J1/46

  using a capacitor · CPC title

• H03M1/50

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title

• G01J5/22 Primary

  Electrical features thereof · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title