Method of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-10032890-B2
Application number	US-201615361516-A
Country	US
Kind code	B2
Filing date	Nov 28, 2016
Priority date	Dec 8, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming an insulation pattern on a substrate such that the insulation pattern is covered by a protection pattern and has a gate trench through which an active region of the substrate is partially exposed;
sequentially forming a gate dielectric layer and a work function metal layer on the substrate along a surface profile of the gate trench such that the protection pattern is covered by the gate dielectric layer;
forming a sacrificial layer on the work function metal layer to fill the gate trench;
planarizing the sacrificial layer without exposing the insulation pattern to thereby form a sacrificial pattern in the gate trench;
forming a residual sacrificial pattern in the gate trench by removing an upper portion of the sacrificial pattern; and
partially removing the work function metal layer and the gate dielectric layer to form a gate dielectric pattern and a work function metal pattern such that upper surfaces of the gate dielectric pattern and the work function metal pattern are coplanar with an upper surface of the residual sacrificial pattern.

2. The method as claimed in claim 1 , wherein planarizing the sacrificial layer is performed by a planarization process using one of the work function metal layer and the gate dielectric layer as a planarization stop layer.

3. The method as claimed in claim 2 , wherein the work function metal layer is a multilayer structure including first to third metal layers, and the sacrificial layer is planarized until the third metal layer of the work function metal layer is exposed.

4. The method as claimed in claim 2 , wherein the gate dielectric layer includes a high-k material having a dielectric constant greater than that of silicon oxide.

5. The method as claimed in claim 2 , wherein the gate dielectric pattern and the work function metal pattern have upper surfaces that are substantially coplanar with an upper surface of the residual sacrificial pattern.

6. The method as claimed in claim 1 , wherein planarizing the sacrificial layer is performed by a planarization process using the protection pattern as a planarization stop layer.

7. The method as claimed in claim 6 , wherein the protection pattern includes a silicon nitride pattern that is formed on the insulation pattern by an atomic layer deposition (ALD) process.

8. The method as claimed in claim 7 , wherein the work function metal pattern has an upper surface that is substantially coplanar with an upper surface of the residual sacrificial pattern.

9. The method as claimed in claim 1 , wherein the sacrificial layer includes an organic layer without silicon (Si).

10. The method as claimed in claim 9 , wherein the organic layer includes one of spin-on-carbon (SOC) layer and a spin-on-hard mask (SOH) layer that are coated on the substrate by a spin-on coating process.

11. A method of manufacturing a semiconductor device, the method comprising:
forming a preliminary gate structure on a substrate, the preliminary gate structure having a dummy gate line extending in a second direction and partially covering an active fin, which is protruded from the substrate into a line extending in a first direction, and forming source/drain junctions arranged at surface portions of the active fin and separated from the dummy gate line by a gate spacer;
forming an insulation interlayer pattern covering the source/drain junctions and exposing the dummy gate line and the gate spacer;
forming a protection pattern on the insulation interlayer pattern;
removing the dummy gate line from the substrate, thereby forming a gate trench through which the active fin is partially exposed;
sequentially forming a gate dielectric layer and a work function metal layer on the substrate along a surface profile of the gate trench such that the protection pattern is covered by the gate dielectric layer;
forming a sacrificial layer on the work function metal layer to a thickness to fill the gate trench;
planarizing the sacrificial layer without exposing the insulation interlayer pattern and the gate spacer, thereby forming a sacrificial pattern in the gate trench;
forming a gate dielectric pattern and a work function metal pattern in the gate trench by node-separating the gate dielectric layer and the work function metal layer by the gate trench; and
forming a gate conductive pattern in the gate trench after a removal of the sacrificial pattern, thereby forming a gate structure having the gate dielectric pattern, the work function metal pattern, and the gate conductive pattern.

12. The method as claimed in claim 11 , wherein planarizing the sacrificial layer is performed by a planarization process in which one of the protection pattern, the gate dielectric pattern, and the work function metal pattern is used as a planarization stop layer.

13. The method as claimed in claim 11 , wherein forming the gate dielectric pattern and the work function metal pattern includes:
partially removing the sacrificial pattern from the substrate, thereby forming a residual sacrificial pattern at a lower portion of the gate trench; and
partially removing the work function metal layer together with the gate dielectric layer by an etching process using the residual sacrificial pattern as an etch stop layer, thereby forming the work function metal pattern and the gate dielectric pattern of which upper surfaces are coplanar with an upper surface of the residual sacrificial pattern.

14. The method as claimed in claim 11 , wherein forming the gate dielectric pattern and the work function metal pattern includes:
removing the work function metal layer together with the sacrificial layer by a planarization process, thereby forming the work function metal pattern simultaneously with the sacrificial pattern;
partially removing the sacrificial pattern from the substrate, thereby forming a residual sacrificial pattern at a lower portion of the gate trench; and
partially removing the gate dielectric layer together with the work function metal pattern by an etching process using the residual sacrificial pattern as an etch stop layer, thereby forming the gate dielectric pattern of which an upper surface is coplanar with upper surfaces of the residual sacrificial pattern and the work function metal pattern.

15. The method as claimed in claim 11 , wherein forming the gate dielectric pattern and the work function metal pattern includes:
removing the work function metal layer and the gate dielectric layer together with the sacrificial layer by a planarization process, thereby forming the gate dielectric pattern and the work function metal pattern simultaneously with the sacrificial pattern;
partially removing the sacrificial pattern from the substrate, thereby forming a residual sacrificial pattern at a lower portion of the gate trench; and
partially removing the work function metal pattern by an etching process using the residual sacrificial pattern as an etch stop layer such that an upper surface of the work function metal pattern is coplanar with an upper surface of the residual sacrificial pattern while sidewalls of the gate trench is covered with the gate dielectric pattern.

16. A method of manufacturing a semiconductor device, the method comprising:
forming an insulation pattern on a substrate, the insulation pattern having first and second gate trenches therein, the first and second gate trenches exposing an active region of the substrate at the bottom of the trenches, the first trenches being in a first region, the second trenches being in a second region, the fir

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yim Jun-Hwan
• Ryu Yeon-Tack
• Han Joo-Cheol
• Koo Ja-Eung
• KIM No-Ul
• Kim Ho-Young
• Yoon Bo-Un

Classifications

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title