Methods for fabricating integrated circuits

Patent metadata

Field	Value
Publication number	US-9136175-B2
Application number	US-201314027837-A
Country	US
Kind code	B2
Filing date	Sep 16, 2013
Priority date	Sep 13, 2011
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

First claim

What is claimed is:

1. A method for fabricating an integrated circuit comprising:
in a bulk silicon substrate, forming a first device area and a second device area, the first device area separated from the second device area by shallow trench isolation;
dividing the first device area into a plurality of spaced apart silicon fins separated by a shallow trench isolation insulator;
epitaxially growing a layer of undoped channel silicon over portions of the first device area and t…

Assignees

• Globalfoundries Inc

Inventors

• Wei Andy
• Baars Peter
• Geiss Erik P

Classifications

• H10W20/069

  Electricity · mapped topic

• H10W10/17

  Electricity · mapped topic

• H10W10/014

  Electricity · mapped topic

• H10D84/0193 Primary

  Electricity · mapped topic

• H10D84/0158

  Electricity · mapped topic