Semiconductor die with back-side integrated inductive component

Patent metadata

Field	Value
Publication number	US-10032850-B2
Application number	US-201615152518-A
Country	US
Kind code	B2
Filing date	May 11, 2016
Priority date	May 11, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

An integrated circuit (IC) that includes a circuit substrate having a front side surface and an opposite back side surface. Active circuitry is located on the front side surface. An inductive structure is located within a deep trench formed in the circuit substrate below the backside surface. The inductive structure is coupled to the active circuitry.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a circuit substrate having a front side and an opposite back side;
active circuitry located on the front side; and
an inductive structure embedded within a deep trench formed in the circuit substrate on the back side; and
a package substrate, in which the circuit substrate is mounted on the package substrate such that contact pads of the active circuitry are bump bonded to leads on the package substrate;
the inductive structure being connected to the active circuitry via wire bonds from the leads to contact points on the inductive structure.

2. The IC of claim 1 , further including multiple inductive structures embedded in the circuit substrate on the back side configured to inductively couple to each other.

3. The IC of claim 1 , in which the deep trench has a depth in the range of approximately 25-500 um.

4. The IC of claim 1 , in which the deep trench is at least four times as deep as it is wide.

5. The IC of claim 2 , in which the circuit substrate includes a first substrate layer and a second substrate layer separated by an insulating layer, in which a first one of the multiple inductive structures is formed in the first substrate layer and in which a second one of the multiple inductive structures is formed in the second substrate layer.

6. The IC of claim 1 , in which the circuit substrate is a silicon-on-insulator substrate, in which the trench is formed in an insulator portion of the circuit substrate.

7. The IC of claim 1 , in which the package substrate is a lead frame.

8. A system comprising:
a system substrate; and
an integrated circuit (IC) mounted on the system substrate, in which the IC includes:
a circuit substrate having a front side surface and an opposite back side surface;
active circuitry located on the front side surface such that contact pads of the active circuitry are bump bonded to leads on the system substrate; and
an inductive structure located within a deep trench formed in the circuit substrate below the backside surface, in which the inductive structure is coupled to the active circuitry via wire bonds from the leads to contact points on the inductive structure.

9. A method of making an integrated circuit having an integrated inductive component, the method comprising:
fabricating active circuitry on a front side of a circuit substrate of the integrated circuit (IC);
mounting the circuit substrate on a package substrate such that contact pads of the active circuitry are bump bonded to leads on the package substrate;
etching a deep trench into a back side of the circuit substrate;
filling the trench with an electrically conductive material to form a coil; and
coupling the coil to the active circuitry via wire bonds from the leads to contact points on the coil.

10. The method of claim 9 , in which etching a deep trench forms multiple deep trenches for multiple coils configured to inductively couple to each other.

11. The method of claim 9 , further including forming through silicon vias (TSV) to couple the coil to the active circuitry.

12. The method of claim 9 , in which the deep trench is etched to a depth within a range of approximately 25-500 um.

13. The method of claim 10 , in which the circuit substrate includes a first substrate layer and a second substrate layer separated by an insulating layer, in which a first one of the multiple coils is formed in the first substrate layer; and further including:
etching a second deep trench into the second substrate layer;
filling the second trench with an electrically conductive material to form a second coil; and
coupling the second coil to the active circuitry.

14. The method of claim 9 , in which the circuit substrate is a silicon-on-insulator substrate, in which the trench is etched in an insulator portion of the circuit substrate.

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Massolini Roberto Giampiero
• Carothers Daniel

Classifications

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title