Semiconductor package structure

Patent metadata

Field	Value
Publication number	US-10032692-B2
Application number	US-201313797637-A
Country	US
Kind code	B2
Filing date	Mar 12, 2013
Priority date	Mar 12, 2013
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

First claim

The invention claimed is:

1. A semiconductor package structure comprising:
a substrate comprising a surface;
a semiconductor die comprising a first surface connected to the surface of the substrate and a second surface that is not connected to the surface of the substrate;
a mold compound on the substrate and surrounding the semiconductor die,
at least one capacitor connected to the surface of the substrate, wherein the mold compound surrounds the at least one capacitor;
wherein the second surface of the semiconductor die is exposed from the mold compound;
wherein a surface of the at least one capacitor is exposed from the mold compound;
wherein the second surface of the semiconductor die, the exposed surface of the at least one capacitor, and a surface of the mold compound are substantially planar; and
a heat dissipation cover attached to the second surface of the semiconductor die and the mold compound.

2. The semiconductor package structure of claim 1 , wherein the mold compound is on substantially an entirety of the surface of the substrate that is exposed from the semiconductor die and the at least one capacitor.

3. The semiconductor package structure of claim 1 , wherein a surface of the heat dissipation cover that attaches to the semiconductor die and the mold compound is substantially flat.

4. The semiconductor package structure of claim 1 , wherein the heat dissipation cover is spaced apart from the surface of the substrate.

5. The semiconductor package structure of claim 1 , wherein the heat dissipation cover does not extend below a plane of the second surface of the semiconductor die towards the substrate.

6. The semiconductor package structure of claim 1 , wherein the first surface of the semiconductor die is connected to the substrate via an underfill material.

7. A semiconductor package structure comprising:
a substrate comprising a surface;
a semiconductor die comprising a first surface connected to the surface of the substrate and a second surface that is not connected to the surface of the substrate;
at least one capacitor connected to the surface of the substrate;
a mold compound on the substrate surrounding the semiconductor die, wherein the second surface of the semiconductor die and a surface of the at least one capacitor are exposed from the mold compound;
wherein the second surface of the semiconductor die, exposed surface of the at least one capacitor, and a surface of the mold compound are substantially planar; and
a heat dissipation cover attached to the second surface of the semiconductor die, the exposed surface of the at least one capacitor, and the surface of the mold compound.

8. The semiconductor package structure of claim 7 , wherein the mold compound is on substantially an entirety of an exposed surface of the substrate surrounding the semiconductor die and the at least one capacitor.

9. The semiconductor package structure of claim 7 , wherein a surface of the heat dissipation cover that attaches to the second surface of the semiconductor die, the exposed surface of the at least one capacitor, and the surface of the mold compound is substantially flat.

10. The semiconductor package structure of claim 7 , wherein the heat dissipation cover does not extend perpendicularly beyond the second surface of the semiconductor die towards the substrate.

11. The semiconductor package structure of claim 7 , wherein the heat dissipation cover is spaced apart from the surface of the substrate.

12. A packaged semiconductor device comprising:
a substrate comprising a surface;
a semiconductor die comprising a first surface connected to the surface of the substrate and a second surface that is not connected to the surface of the substrate;
at least one capacitor comprising a first surface connected to the surface of the substrate and a second surface that is not connected to the surface of the substrate;
a mold compound comprising a first surface connected to the surface of the substrate and a second surface that is not connected to the surface of the substrate, the mold compound surrounding the semiconductor die and the at least one capacitor;
wherein the second surface of the semiconductor die, second surface of the at least one capacitor, and second surface of the mold compound are substantially planar; and
a heat dissipation cover comprising a continuous flat surface, wherein said continuous flat surface is attached to the second surface of the semiconductor die, to the second surface of the at least one capacitor, and the second surface of the mold compound.

Assignees

• Nvidia Corp

Inventors

• Kalchuri Shantanu
• Schieck Brian
• Yee Abraham

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W76/67

  characterised by their materials · CPC title