IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures
US-11495568-B2 · Nov 8, 2022 · US
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Schieck Brian patents
Schieck Brian is listed as an inventor on 5 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Schieck Brian |
| Total patents | 5 |
| First publication | Jul 24, 2018 |
| Latest publication | Nov 8, 2022 |
Notable patents
Publications ranked by popularity score, then publication date.
Ic package design and methodology to compensate for die-substrate cte mismatch at reflow temperatures
US-2021151403-A1 · May 20, 2021 · US
IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures
US-10943882-B1 · Mar 9, 2021 · US
Ic package design and methodology to compensate for die-substrate cte mismatch at reflow temperatures
US-2021066227-A1 · Mar 4, 2021 · US
Semiconductor package structure
US-10032692-B2 · Jul 24, 2018 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Nvidia Corp | 5 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/724 | 5 |
| H10W72/072 | 5 |
| H10W72/29 | 4 |
| H10W72/952 | 4 |
| H10W72/923 | 4 |