Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-2016173097-A1
Application number	US-201514967592-A
Country	US
Kind code	A1
Filing date	Dec 14, 2015
Priority date	Dec 16, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. When the semiconductor device returns to a normal state, the second potential is supplied, so that the potential of a node in the level shifter circuit increases. To utilize the increase in the second potential or suppress malfunction due to the increase in the potential, capacitors are provided in the level shifter circuit. This inhibits unexpected operation of a transistor in the level shifter circuit.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first wiring configured to supply a first potential; a second wiring configured to supply a second potential, the second potential being higher than the first potential; a third wiring configured to supply a third potential, the third potential being lower than the first potential and the second potential; a first buffer circuit electrically connected to the first wiring and the third wiring; and a level shifter circuit electrically connected to the second wiring and the third wiring, the level shifter circuit comprising a first node and a second node, wherein the first node is configured to hold the second potential when a low-level potential is output from the level shifter circuit, wherein the second node is configured to hold the third potential when the low-level potential is output from the level shifter circuit, and wherein the level shifter circuit comprises:
a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the second wiring, and wherein a second electrode of the first capacitor is electrically connected to the first node; and
a second capacitor, wherein a first electrode of the second capacitor is electrically connected to the third wiring, and wherein a second electrode of the second capacitor is electrically connected to the second node.

2 . The semiconductor device according to claim 1 , wherein the third potential is a ground potential.

3 . The semiconductor device according to claim 1 ,
wherein the level shifter circuit further comprises a first transistor, and wherein a channel formation region of the first transistor comprises silicon.

4 . The semiconductor device according to claim 1 ,
wherein the level shifter circuit further comprises a first transistor, and wherein the first capacitor and the second capacitor are provided over the first transistor.

5 . The semiconductor device according to claim 1 , further comprising a memory cell,
wherein the memory cell comprises a second transistor, and wherein a channel formation region of the second transistor comprises an oxide semiconductor.

6 . The semiconductor device according to claim 1 , further comprising a memory cell,
wherein the memory cell comprises a second transistor, and wherein a gate of the second transistor is electrically connected to the level shifter circuit.

7 . The semiconductor device according to claim 1 , further comprising a memory cell,
wherein the memory cell comprises a third capacitor, wherein a first electrode of the third capacitor is provided in the same layer as the first electrode of the first capacitor and the first electrode of the second capacitor, and wherein a second electrode of the third capacitor is provided in the same layer as the second electrode of the first capacitor and the second electrode of the second capacitor.

8 . An electronic device comprising the semiconductor device according to claim 1 .

9 . A semiconductor device comprising:
a first wiring configured to supply a first potential; a second wiring configured to supply a second potential, the second potential being higher than the first potential; a third wiring configured to supply a third potential, the third potential being lower than the first potential and the second potential; a first buffer circuit electrically connected to the first wiring and the third wiring; a level shifter circuit electrically connected to the second wiring and the third wiring, the level shifter circuit comprising a first node and a second node; and a second buffer circuit electrically connected to the second wiring and the third wiring, wherein the first node is configured to hold the second potential when a low-level potential is output from the level shifter circuit to the second buffer circuit, wherein the second node is configured to hold the third potential when the low-level potential is output from the level shifter circuit to the second buffer circuit, and wherein the level shifter circuit comprises:
a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the second wiring, and wherein a second electrode of the first capacitor is electrically connected to the first node; and
a second capacitor, wherein a first electrode of the second capacitor is electrically connected to the third wiring, and wherein a second electrode of the second capacitor is electrically connected to the second node.

10 . The semiconductor device according to claim 9 , wherein the third potential is a ground potential.

11 . The semiconductor device according to claim 9 ,
wherein the level shifter circuit further comprises a first transistor, and wherein a channel formation region of the first transistor comprises silicon.

12 . The semiconductor device according to claim 9 ,
wherein the level shifter circuit further comprises a first transistor, and wherein the first capacitor and the second capacitor are provided over the first transistor.

13 . The semiconductor device according to claim 9 , further comprising a memory cell,
wherein the memory cell comprises a second transistor, and wherein a channel formation region of the second transistor comprises an oxide semiconductor.

14 . The semiconductor device according to claim 9 , further comprising a memory cell,
wherein the memory cell comprises a second transistor, and wherein a gate of the second transistor is electrically connected to the second buffer circuit.

15 . The semiconductor device according to claim 9 , further comprising a memory cell,
wherein the memory cell comprises a third capacitor, wherein a first electrode of the third capacitor is provided in the same layer as the first electrode of the first capacitor and the first electrode of the second capacitor, and wherein a second electrode of the third capacitor is provided in the same layer as the second electrode of the first capacitor and the second electrode of the second capacitor.

16 . An electronic device comprising the semiconductor device according to claim 9 .

Assignees

• Semiconductor Energy Lab

Inventors

• Inoue Hiroki
• Matsuzaki Takanori
• Nagatsuka Shuhei
• Ishizu Takahiko
• Onuki tatsuya

Classifications

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title