Semiconductor device, sensor device, and electronic device

Patent metadata

Field	Value
Publication number	US-2016178409-A1
Application number	US-201514971636-A
Country	US
Kind code	A1
Filing date	Dec 16, 2015
Priority date	Dec 18, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A novel semiconductor device or a semiconductor device whose power consumption can be reduced is provided. The semiconductor device includes a sensor portion, a memory portion, and a control portion. The memory portion has functions of storing multiple detection data and sending them to the control portion. Therefore, a certain amount of detection data acquired through sensing by the sensor portion can be held, and the detection data can be sent to the control portion at a desired timing. Accordingly, in the semiconductor device, the control portion does not need to operate every time information is acquired, and thus, the power supply to the control portion can be completely or partially stopped.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first circuit; a second circuit; and a third circuit, wherein the first circuit is configured to acquire information from outside, wherein the second circuit is configured to store data corresponding to the information acquired by the first circuit, wherein the third circuit is configured to process the data, wherein the third circuit is configured to be in a resting state in at least a part of a period in which an amount of the data stored in the second circuit is below a reference value, and wherein the second circuit is configured to output the data to the third circuit when the amount of the data stored in the second circuit reaches the reference value.

2 . The semiconductor device according to claim 1 ,
wherein the second circuit comprises a control circuit and a memory circuit, wherein the control circuit is configured to control data writing to the memory circuit and data reading from the memory circuit, and wherein the memory circuit is configured to be in a resting state in at least a part of a period in which neither data writing nor data reading is performed.

3 . The semiconductor device according to claim 2 ,
wherein the second circuit further comprises a switch circuit, wherein the switch circuit is electrically connected to a power supply line and the memory circuit, and wherein the memory circuit is brought into the resting state when the switch circuit is turned off.

4 . The semiconductor device according to claim 2 ,
wherein the memory circuit comprises a memory region and a counter, wherein the counter is configured to count the number of sets of the data stored in the memory region, wherein the memory region comprises a transistor and a capacitor, wherein one of a source and a drain of the transistor is electrically connected to the capacitor, and wherein a channel formation region of the transistor comprises an oxide semiconductor.

5 . The semiconductor device according to claim 1 , wherein the third circuit comprises a power management unit and a central processing unit.

6 . A sensor device comprising the semiconductor device according to claim 1 .

7 . An electronic device comprising the semiconductor device according to claim 1 , wherein the electronic device comprises at least one of a lens, a display portion, and an operation key.

8 . An electronic device comprising the sensor device according to claim 6 , wherein the electronic device comprises at least one of a lens, a display portion, and an operation key.

9 . The semiconductor device according to claim 1 ,
wherein the second circuit comprises:
a control circuit;
a memory circuit; and
a switch circuit,
wherein the control circuit is configured to control data writing to the memory circuit and data reading from the memory circuit, wherein the memory circuit is configured to be in a resting state in at least a part of a period in which neither data writing nor data reading is performed, wherein the switch circuit is electrically connected to a power supply line and the memory circuit, wherein the memory circuit is brought into the resting state when the switch circuit is turned off, wherein the memory circuit comprises a memory region and a counter, wherein the counter is configured to count the number of sets of the data stored in the memory region, wherein the memory region comprises a transistor and a capacitor, wherein one of a source and a drain of the transistor is electrically connected to the capacitor, and wherein a channel formation region of the transistor comprises an oxide semiconductor.

Assignees

• Semiconductor Energy Lab

Inventors

• Tsutsui Naoaki

Classifications

• H02J13/1323 Primary

  using optical fibres · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H01L29/7869

  Electricity · mapped topic

• H02J1/00

  Circuit arrangements for DC mains or DC distribution networks · CPC title

• G01D9/32 Primary

  there being a common recording element for two or more variables · CPC title