Semiconductor device with isolated body portion

Patent metadata

Field	Value
Publication number	US-10026829-B2
Application number	US-201715434981-A
Country	US
Kind code	B2
Filing date	Feb 16, 2017
Priority date	Dec 20, 2011
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a semiconductor fin protruding from a semiconductor substrate, the semiconductor fin comprising an upper portion and a lower portion, the upper portion having a channel region;
an insulating region between the upper portion of the semiconductor fin and the lower portion of the semiconductor fin, the insulating region having an approximately vertical seam approximately between a center of the upper portion of the semiconductor fin and a center of the lower portion of the semiconductor fin;
a gate electrode over a top surface of the channel region of the upper portion of the semiconductor fin and adjacent sidewall surfaces of the channel region of the upper portion of the semiconductor fin;
a source region adjacent the channel region at a first side of the gate electrode; and
a drain region adjacent the channel region at a second side of the gate electrode opposite the first side of the gate electrode.

2. The integrated circuit structure of claim 1 , wherein the approximately vertical seam of the insulating is between a downward protruding point of the upper portion of the semiconductor fin and an upward protruding point of the lower portion of the semiconductor fin.

3. The integrated circuit structure of claim 1 , wherein the insulating region comprises an uppermost surface above a top surface of a portion of the insulating region between the upper portion of the semiconductor fin and the lower portion of the semiconductor fin.

4. The integrated circuit structure of claim 1 , wherein the lower portion of the semiconductor fin is continuous with the semiconductor substrate.

5. The integrated circuit structure of claim 1 , wherein the insulating region electrically isolates the upper portion of the semiconductor fin from the lower portion of the semiconductor fin.

6. The integrated circuit structure of claim 1 , wherein the semiconductor fin is a silicon semiconductor fin.

7. The integrated circuit structure of claim 6 , wherein the insulating region comprises an oxide of silicon germanium.

8. The integrated circuit structure of claim 1 , wherein the gate electrode comprises a metal.

9. The integrated circuit structure of claim 1 , further comprising a high-K gate dielectric layer between the gate electrode and the channel region of the upper portion of the semiconductor fin.

10. The integrated circuit structure of claim 1 , further comprising:
one or more nanowires vertically above the upper portion of the semiconductor fin, wherein the gate electrode at least partially surrounds a portion of each of the one or more nanowires.

11. A method of fabricating an integrated circuit structure, the method comprising:
forming a semiconductor body above a semiconductor substrate, the semiconductor body comprising a channel region and a pair of source and drain regions on either side of the channel region;
forming an isolation pedestal between the semiconductor body and the semiconductor substrate, wherein the semiconductor body comprises a first semiconductor material and the isolation pedestal comprises an oxide of a second semiconductor material different from the first semiconductor material and an approximately vertical seam centered within the isolation pedestal, the approximately vertical seam continuous between the semiconductor body and the semiconductor substrate; and
forming a gate electrode stack at least partially surrounding a portion of the channel region of the semiconductor body.

12. The method of claim 11 , wherein the isolation pedestal is formed below the channel region, but not below the pair of source and drain regions, of the semiconductor body.

13. The method of claim 11 , wherein the isolation pedestal is formed below the pair of source and drain regions, but not below the channel region, of the semiconductor body.

14. The method of claim 11 , wherein the isolation pedestal is formed below the pair of source and drain regions and below the channel region of the semiconductor body.

15. The method of claim 11 , further comprising:
forming a first dielectric layer adjacent to the isolation pedestal and above the semiconductor substrate; and
forming a second dielectric layer below the first dielectric layer and on the semiconductor substrate.

16. An integrated circuit structure, comprising:
a semiconductor fin protruding from a semiconductor substrate, the semiconductor fin comprising an upper portion and a lower portion, the upper portion having a channel region;
an insulating region between the upper portion of the semiconductor fin and the lower portion of the semiconductor fin, the insulating region between a downward protruding flat surface of the upper portion of the semiconductor fin and an upward protruding flat surface of the lower portion of the semiconductor fin;
a gate electrode over a top surface of the channel region of the upper portion of the semiconductor fin and adjacent sidewall surfaces of the channel region of the upper portion of the semiconductor fin;
a source region adjacent the channel region at a first side of the gate electrode; and
a drain region adjacent the channel region at a second side of the gate electrode opposite the first side of the gate electrode.

17. The integrated circuit structure of claim 16 , wherein the insulating region comprises a laterally continuous material on between the downward protruding flat surface of the upper portion of the semiconductor fin and the upward protruding flat surface of the lower portion of the semiconductor fin.

18. The integrated circuit structure of claim 16 , wherein the insulating region comprises an uppermost surface above a top surface of a portion of the insulating region between the upper portion of the semiconductor fin and the lower portion of the semiconductor fin.

19. The integrated circuit structure of claim 16 , wherein the lower portion of the semiconductor fin is continuous with the semiconductor substrate.

20. The integrated circuit structure of claim 16 , wherein the insulating region electrically isolates the upper portion of the semiconductor fin from the lower portion of the semiconductor fin.

21. The integrated circuit structure of claim 16 , wherein the semiconductor fin is a silicon semiconductor fin.

22. The integrated circuit structure of claim 21 , wherein the insulating region comprises an oxide of silicon germanium.

23. The integrated circuit structure of claim 16 , wherein the gate electrode comprises a metal.

24. The integrated circuit structure of claim 16 , further comprising a high-K gate dielectric layer between the gate electrode and the channel region of the upper portion of the semiconductor fin.

25. The s integrated circuit structure of claim 16 , further comprising:
one or more nanowires vertically above the upper portion of the semiconductor fin, wherein the gate electrode at least partially surrounds a portion of each of the one or more nanowires.

Assignees

• Intel Corp

Inventors

• Cappellani Annalisa
• Cea Stephen M
• Ghani Tahir
• Gomez Harry
• Kavalieros Jack T
• Keys Patrick H
• Kim Seiyon
• Kuhn Kelin J
• Lilak Aaron D
• Rios Rafael
• Sahni Mayank

Classifications

• H10W10/0126

  introducing electrical active impurities in local oxidation regions to create channel stoppers · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title