Semiconductor device with isolated body portion

Patent metadata

Field	Value
Publication number	US-9608059-B2
Application number	US-201113995418-A
Country	US
Kind code	B2
Filing date	Dec 20, 2011
Priority date	Dec 20, 2011
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor body disposed above a semiconductor substrate, the semiconductor body having a first width and comprising a channel region and a pair of source and drain regions on either side of the channel region;
an isolation pedestal disposed between the semiconductor body and the semiconductor substrate, the isolation pedestal having a second width parallel with, and less than, the first width, wherein the isolation pedestal is an electrically insulating isolation pedestal, the isolation pedestal completely electrically isolating the semiconductor body from the semiconductor substrate; and
a gate electrode stack at least partially surrounding a portion of the channel region of the semiconductor body.

2. The semiconductor device of claim 1 , wherein the isolation pedestal is disposed below the channel region, but not below the pair of source and drain regions, of the semiconductor body.

3. The semiconductor device of claim 1 , wherein the isolation pedestal is disposed below the pair of source and drain regions, but not below the channel region, of the semiconductor body.

4. The semiconductor device of claim 1 , wherein the isolation pedestal is disposed below the pair of source and drain regions and below the channel region of the semiconductor body.

5. The semiconductor device of claim 1 , wherein the isolation pedestal is notched with rounded edges beneath the semiconductor body.

6. The semiconductor device of claim 1 , wherein the isolation pedestal is notched with faceted edges beneath the semiconductor body.

7. The semiconductor device of claim 1 , further comprising:
a first dielectric layer disposed adjacent to the isolation pedestal and above the semiconductor substrate.

8. The semiconductor device of claim 7 , further comprising:
a second dielectric layer disposed below the first dielectric layer and on the semiconductor substrate.

9. The semiconductor device of claim 1 , wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric.

10. The semiconductor device of claim 1 , further comprising:
one or more nanowires disposed vertically above the semiconductor body, wherein the gate electrode stack at least partially surrounds a portion of each of the one or more nanowires.

11. A semiconductor device, comprising:
a semiconductor body disposed above a semiconductor substrate, the semiconductor body comprising a first semiconductor material, and comprising a channel region and a pair of source and drain regions on either side of the channel region;
an isolation pedestal disposed between the semiconductor body and the semiconductor substrate, the isolation pedestal comprising an oxide of a second semiconductor material different from the first semiconductor material, wherein the isolation pedestal is an electrically insulating isolation pedestal, the isolation pedestal completely electrically isolating the semiconductor body from the semiconductor substrate; and
a gate electrode stack at least partially surrounding a portion of the channel region of the semiconductor body.

12. The semiconductor device of claim 11 , wherein the isolation pedestal is disposed below the channel region, but not below the pair of source and drain regions, of the semiconductor body.

13. The semiconductor device of claim 11 , wherein the isolation pedestal is disposed below the pair of source and drain regions, but not below the channel region, of the semiconductor body.

14. The semiconductor device of claim 11 , wherein the isolation pedestal is disposed below the pair of source and drain regions and below the channel region of the semiconductor body.

15. The semiconductor device of claim 11 , wherein the semiconductor body consists essentially of silicon, and the second semiconductor material is silicon germanium.

16. The semiconductor device of claim 11 , further comprising:
a dielectric layer disposed adjacent to the isolation pedestal and above the semiconductor substrate.

17. The semiconductor device of claim 16 , further comprising:
a second dielectric layer disposed below the first dielectric layer and on the semiconductor substrate.

18. The semiconductor device of claim 11 , wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric.

19. The semiconductor device of claim 11 , further comprising:
one or more nanowires disposed vertically above the semiconductor body, wherein the gate electrode stack at least partially surrounds a portion of each of the one or more nanowires.

20. The semiconductor device of claim 11 , wherein the semiconductor body has a first width, and the isolation pedestal has a second width parallel with and less than the first width.

21. The semiconductor device of claim 20 , wherein the isolation pedestal is notched with rounded edges beneath the semiconductor body.

22. The semiconductor device of claim 20 , wherein the isolation pedestal is notched with faceted edges beneath the semiconductor body.

23. A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor body above a semiconductor substrate, the semiconductor body comprising a channel region and a pair of source and drain regions on either side of the channel region;
forming an isolation pedestal between the semiconductor body and the semiconductor substrate, wherein the semiconductor body has a first width and the isolation pedestal is formed from a second width parallel with and less than the first width or wherein the semiconductor body comprises a first semiconductor material and the isolation pedestal comprises an oxide of a second semiconductor material different from the first semiconductor material, wherein the isolation pedestal is an electrically insulating isolation pedestal, the isolation pedestal completely electrically isolating the semiconductor body from the semiconductor substrate; and
forming a gate electrode stack at least partially surrounding a portion of the channel region of the semiconductor body.

24. The method of claim 23 , wherein the isolation pedestal is formed below the channel region, but not below the pair of source and drain regions, of the semiconductor body.

25. The method of claim 23 , wherein the isolation pedestal is formed below the pair of source and drain regions, but not below the channel region, of the semiconductor body.

26. The method of claim 23 , wherein the isolation pedestal is formed below the pair of source and drain regions and below the channel region of the semiconductor body.

27. The method of claim 23 , further comprising:
forming a first dielectric layer adjacent to the isolation pedestal and above the semiconductor substrate.

28. The method of claim 27 , further comprising:
forming a second dielectric layer below the first dielectric layer and on the semiconductor substrate.

Assignees

• Cappellani Annalisa
• Cea Stephen M
• Ghani Tahir
• Gomez Harry
• Kavalieros Jack T
• Keys Patrick H
• Kim Seiyon
• Kuhn Kelin J
• Lilak Aaron D
• Rios Rafael
• Sahni Mayank
• Intel Corp

Inventors

• Cappellani Annalisa
• Cea Stephen M
• Ghani Tahir
• Gomez Harry
• Kavalieros Jack T
• Keys Patrick H
• Kim Seiyon
• Kuhn Kelin J
• Lilak Aaron D
• Rios Rafael
• Sahni Mayank

Classifications

• H10W10/0126

  introducing electrical active impurities in local oxidation regions to create channel stoppers · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title