Method for manufacturing a bipolar junction transistor

Patent metadata

Field	Value
Publication number	US-10020387-B2
Application number	US-201715452780-A
Country	US
Kind code	B2
Filing date	Mar 8, 2017
Priority date	May 2, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

Embodiments provide a method for manufacturing a bipolar junction transistor, comprising:
providing a semiconductor substrate comprising a buried layer of a first conductive type; doping the semiconductor substrate in a collector implant region, to obtain a collector implant of the first conductive type extending parallel to a surface of the semiconductor substrate and from the surface of the semiconductor substrate to the buried layer; providing a base layer of a second conductive type on the surface of the semiconductor substrate, the base layer covering the collector implant; providing a sacrificial emitter structure on the base layer, wherein a projection of an area of the sacrificial emitter structure is enclosed by an area of the collector implant; and partially counter doping the collector implant through an area of the base layer surrounding an area of the base layer that is covered by the sacrificial emitter structure.

First claim

What is claimed is:

1. A method for manufacturing a bipolar junction transistor, the method comprising:
providing a semiconductor substrate comprising a buried layer of a first conductive type;
doping the semiconductor substrate, in a collector implant region, to obtain a collector implant of the first conductive type extending parallel to a surface of the semiconductor substrate and from the surface of the semiconductor substrate to the buried layer;
providing a base layer of a second conductive type on the surface of the semiconductor substrate, the base layer covering the collector implant;
providing a sacrificial emitter structure on the base layer, wherein a projection of an area of the sacrificial emitter structure is enclosed by an area of the collector implant; and
partially counter doping the collector implant through an area of the base layer surrounding an area of the base layer that is covered by the sacrificial emitter structure to generate a counter doped collector implant region of the collector implant.

2. The method according to claim 1 , wherein the semiconductor substrate comprises trenches extending from the surface of the semiconductor substrate into a depth direction of the semiconductor substrate; and
wherein doping the semiconductor substrate comprises doping the semiconductor substrate in a collector implant region between the trenches.

3. The method according to claim 2 , wherein doping the semiconductor substrate comprises doping the semiconductor substrate, in a collector implant region that completely extends between the trenches, to obtain a collector implant completely extending between the trenches.

4. The method according to claim 1 , wherein doping the semiconductor substrate comprises providing a cap layer and partly opening the cap layer, to obtain an opening that defines the collector implant region.

5. The method according to claim 1 , wherein providing the base layer comprises epitaxially growing the base layer on the surface of the semiconductor substrate at least in an area adjacent to the collector implant.

6. The method according to claim 1 , wherein providing the sacrificial emitter structure comprises providing an isolation layer on the base layer and providing a sacrificial emitter layer on the isolation layer.

7. The method according to claim 6 , wherein providing the sacrificial emitter structure comprises partially removing the sacrificial emitter layer to obtain a sacrificial emitter, wherein a projection of an area of the sacrificial emitter is enclosed by the area of the collector implant.

8. The method according to claim 7 , wherein providing the sacrificial emitter structure comprises providing lateral isolation layers on sidewalls of the sacrificial emitter.

9. The method according to claim 8 , wherein providing the sacrificial emitter structure comprises partially removing the isolation layer such that the isolation layer protrudes under the sacrificial emitter and such that a projection of an area of the isolation layer is enclosed by the area of the collector implant.

10. The method according to claim 9 , wherein providing the sacrificial emitter structure comprises providing an isolation spacer on the isolation layer and the lateral isolation layers, to obtain the sacrificial emitter structure.

11. The method according to claim 1 , wherein the method comprises providing a base contact layer on the base layer.

12. The method according to claim 1 ,
wherein the sacrificial emitter structure comprises a sacrificial emitter;
wherein the method further comprises removing the sacrificial emitter to obtain an emitter window, and
wherein a projection of an area of the emitter window is enclosed by the area of the collector implant.

13. The method according to claim 12 , wherein the method comprises providing an emitter layer of the first conductive type in the emitter window to obtain an emitter.

14. The method according to claim 12 , wherein the sacrificial emitter structure comprises an isolation layer arranged between the sacrificial emitter and the base layer,
wherein the isolation layer protrudes under the sacrificial emitter and such that a projection of an area of the isolation layer is enclosed by the area of the collector implant;
wherein the method further comprises removing the sacrificial emitter and the isolation layer, to obtain an emitter window, and
wherein the emitter window protrudes under isolation spacers and wherein a projection of an area of the emitter window is enclosed by the area of the collector implant.

15. The method according to claim 12 , wherein the method further comprises providing an emitter layer of the first conductive type on a base contact layer and in the emitter window such that an overfill of the emitter window is achieved.

16. The method according to claim 15 , wherein the sacrificial emitter protrudes under the base contact layer in notches obtained by removing an isolation layer which protruded under isolation spacers.

17. The method according to claim 16 , wherein the method further comprises partially removing the emitter layer at least up to the base contact layer, to obtain an emitter in the emitter window.

18. The method according to claim 17 , wherein partially removing the emitter layer at least up to the base contact layer comprises removing the emitter layer at least up to the base contact layer while maintaining the isolation spacers.

19. The method according to claim 17 , further comprising:
providing contacts for contacting the base contact layer and the emitter.

20. The method according to claim 1 , wherein doping the semiconductor substrate in the collector implant region comprises doping the semiconductor substrate in the collector implant region without using a lithographic mask.

21. A bipolar junction transistor, comprising
a semiconductor substrate comprising a buried layer of a first conductive type;
a collector of the first conductive type extending parallel to a surface of the semiconductor substrate and from the surface of the semiconductor substrate to the buried layer;
a base layer of a second conductive type arranged on the surface of the semiconductor substrate, the base layer covering the collector; and
an emitter of the first conductive type arranged on the base layer, wherein the emitter comprises notches arranged directly on the base layer protruding under isolation spacers, wherein a width of the collector is between 0.5 to 2 times the width of the emitter,
wherein the collector is self-aligned to the emitter, and
wherein the collector includes a counter doped collector implant region generated by partially doping the collector through an area of the base layer surrounding an area of the base layer that is covered by the emitter.

Assignees

• Infineon Technologies Dresden Gmbh

Inventors

• Manger Dirk
• Tegen Stefan

Classifications

• H01L29/0649

  Electricity · mapped topic

• H01L29/7378 Primary

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/36

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic