Semiconductor device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-9343554-B2
Application number	US-201414769882-A
Country	US
Kind code	B2
Filing date	Feb 24, 2014
Priority date	Feb 28, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A semiconductor device including a bipolar transistor in which a polysilicon film is used for an emitter electrode. The bipolar transistor includes a collector region formed in an Si substrate, a base layer formed on the collector region, an emitter region formed in an upper part spaced apart from the collector region of the base layers, and a silicon oxide film formed on the base layer and covering a joint portion of the base layer and the emitter region. The density of fluorine existent at an interface between the joint portion and the silicon oxide film is equal to or higher than 1×10 20 cm −3 .

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a collector region formed in a substrate;
a base layer formed on the collector region;
an emitter region formed in an upper part of the base layer;
an insulating film formed on the base layer to partially cover a joint portion of the base layer and the emitter region; and
an emitter electrode made of a polysilicon film formed on the emitter region,
wherein a density of halogen existent at an interface between the joint portion and the insulating film is equal to or higher than 1×10 20 cm −3 .

2. A semiconductor device, comprising:
a collector region formed in a substrate;
a base layer formed on the collector region;
an emitter region formed in an upper part of the base layer;
an insulating film formed on the base layer to cover an end region of the emitter region; and
an emitter electrode made of a polysilicon film formed on the emitter region,
wherein a density of halogen existent at an interface between the end region and the insulating film is equal to or higher than 1×10 20 cm −3 .

3. A semiconductor device, comprising a bipolar transistor in which a polysilicon film is used for an emitter electrode,
the bipolar transistor comprising:
a collector region formed in a substrate;
a base layer formed on the collector region;
an emitter region formed in an upper part of the base layer, the upper part being spaced apart from the collector region; and
an insulating film formed on the base layer to partially cover a joint portion of the base layer and the emitter region;
wherein a density of halogen existent at an interface between the joint portion and the insulating film is equal to or higher than 1×10 20 cm −3 .

4. The semiconductor device according to claim 1 , wherein the density of the halogen existent at a location deeper than the interface between the joint portion and the insulating film is equal to or higher than 1×10 14 cm −3 .

5. The semiconductor device according to claim 1 , wherein the base layer either includes a silicon germanium layer and a silicon layer laminated on the silicon germanium layer, or includes a silicon layer only.

6. The semiconductor device according to claim 1 , wherein the density of an interface between the base layer and the insulating film is equal to or higher than 1×10 20 cm −3 .

7. A manufacturing method of a semiconductor device including a bipolar transistor, the manufacturing method comprising:
implanting impurities of a first conductivity type into a substrate to form a collector region;
forming an impurity layer of a second conductivity type to be a base region on the collector region;
forming a silicon oxide film on the impurity layer of the second conductivity type;
forming a polysilicon film on the silicon oxide film;
doping halogen;
after the halogen is doped, etching the polysilicon film and the silicon oxide film to form an opening portion;
depositing a polysilicon film to form an emitter electrode in the opening portion; and
forming an emitter region in the impurity layer of the second conductivity type.

8. The manufacturing method according to claim 7 , wherein in the step of doping the halogen, after halogen is ion implanted at a dose of equal to or larger than 1×10 15 cm −2 and equal to or smaller than 1×10 16 cm −2 with a peak being set to a vicinity of an interface between the silicon oxide film and the impurity layer of the second conductivity type, an anneal process is conducted.

9. A manufacturing method of a semiconductor device including a bipolar transistor in which a polysilicon film is used for an emitter electrode,
the manufacturing method comprising:
forming a collector region in a substrate;
forming a base layer on the collector region;
forming a silicon oxide film on the base layer;
forming a polysilicon film on the silicon oxide film;
ion implanting halogen at a dose of equal to or larger than 1×10 15 cm −2 and equal to or smaller than 1×10 16 cm −2 into the polysilicon film, the silicon oxide film, and the base layer with a peak being set to a vicinity of an interface between the silicon oxide film and the base layer;
after the halogen is ion implanted, annealing to segregate the halogen at the interface between the silicon oxide film and the base layer;
etching the polysilicon film by using a resist mask;
removing the resist mask;
wet etching the silicon oxide film by using the polysilicon film as a mask to form an opening portion with the base layer being a bottom face;
forming an emitter electrode in the opening portion by depositing a polysilicon film; and
forming an emitter region in an upper part of the base layer by introducing an impurity into the base layer through the opening portion, the upper part being spaced apart from the collector region.

10. The manufacturing method according to claim 9 , wherein the base layer either includes a silicon germanium layer and a silicon layer laminated on the silicon germanium layer, or includes a silicon layer only.

11. The manufacturing method according to claim 9 ,
wherein in the step of forming the emitter electrode in the opening portion, after the polysilicon film is deposited, an impurity of a first conductivity type is implanted, and
wherein in the step of forming the emitter region, an emitter region is formed in the base layer by annealing.

12. The manufacturing method according to claim 9 ,
wherein in the step of forming the emitter electrode in the opening region, the deposited polysilicon film is a doped polysilicon film including the impurity of the first conductivity type, and
wherein in the step of forming the emitter region, the emitter region is formed in the base layer by annealing.

Assignees

• Asahi Kasei Microdevices Corp

Inventors

• Sakamoto Toshiro

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D10/021

  of heterojunction BJTs [HBT] · CPC title

• H10D10/891 Primary

  comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors · CPC title

• H01L29/7378 Primary

  Electricity · mapped topic

• H01L29/66242

  Electricity · mapped topic