Integrated circuit substrate and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10020264-B2
Application number	US-201514698639-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Apr 28, 2015
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.

First claim

What is claimed is:

1. A semiconductor device comprising:
a die substrate originating from a wafer of origin;
an active area disposed at a top main surface of the die substrate; and
a code pattern comprising a sequence of scallops disposed on a sidewall of the die substrate,
wherein each scallop is extended along a longitudinal direction that is essentially parallel to the top main surface of the die substrate, and
wherein the code pattern provides information related to a lot that included the wafer of origin, a position of the die substrate in the wafer of origin, a facility in which the wafer was fabricated or combinations thereof.

2. A method comprising:
detecting a code pattern comprising a sequence of scallops from a sidewall of a semiconductor die, wherein the semiconductor die comprises an integrated circuit, a discrete device or a MEMS device, and wherein each scallop is extended along a longitudinal direction that is essentially parallel to a top main surface of the semiconductor die; and
analyzing the code pattern to obtain information related to a lot that included a wafer of origin, a position of the semiconductor die in the wafer of origin, a facility in which the wafer was fabricated or combinations thereof.

3. The method of claim 2 , wherein detecting the code pattern comprises mechanically detecting the code pattern.

4. The method of claim 2 , wherein detecting the code pattern comprises optically detecting the code pattern.

5. The method of claim 2 , wherein the code pattern is formed in the sidewall as the scallops, each scallop having either a first width or a second width.

6. The method of claim 2 , wherein the scallops are only located in a top portion of the sidewall near the top main surface.

7. The method of claim 2 , wherein the scallops vary in sizes.

8. The semiconductor device of claim 1 , wherein the scallops are only located in a top portion of the sidewall near the top main surface.

9. The semiconductor device of claim 1 , wherein the scallops vary in sizes.

10. The semiconductor device of claim 1 , wherein the die substrate is an integrated circuit.

11. The semiconductor device of claim 1 , wherein the die substrate is a discrete device.

12. The semiconductor device of claim 1 , wherein the die substrate is a MEMS.

13. A semiconductor device comprising:
a die substrate originating from a wafer of origin;
an active area disposed at a top main surface of the die substrate; and
a code pattern comprising a sequence of scallops disposed on a sidewall of the die substrate,
wherein a main extension direction of each scallop is essentially parallel to the top main surface of the die substrate,
wherein the code pattern provides information related to a lot that included the wafer of origin, a position of the die substrate in the wafer of origin, a facility in which the wafer was fabricated or combinations thereof, and
wherein the scallops are only located in a top portion of the sidewall near the top main surface.

14. The semiconductor device of claim 13 , wherein the scallops vary in sizes.

15. The semiconductor device of claim 13 , wherein the die substrate is an integrated circuit.

16. The semiconductor device of claim 13 , wherein the die substrate is a discrete device.

17. The semiconductor device of claim 13 , wherein the die substrate is a MEMS.

Assignees

• Infineon Technologies Ag

Inventors

• Roesner Michael
• Stranzl Gudrun
• Engelhardt Manfred
• Zgaga Martin

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P50/244

  comprising alternated and repeated etching and passivation steps · CPC title

• H10W46/601

  for use after dicing · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/401

  for identification or tracking · CPC title