Shift register unit, gate driver circuit and display panel

Patent metadata

Field	Value
Publication number	US-10019930-B2
Application number	US-201615152811-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	Nov 4, 2015
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

The present disclosure relates to a shift register, a gate driver circuit and a display panel. The shift register includes first to eighth transistors and first and second capacitors. In the exemplary embodiments of the present disclosure, a shift register unit is composed of a relatively small number of transistors and capacitors, and thus the wiring areas occupied by the shift register unit and the gate driver circuit composed of a plurality of the shift register units can be reduced, thereby providing technical support for designing display panels with higher resolution and narrower bezel. Meanwhile, because the shift register unit and the gate driver circuit have a relatively simple structure, the manufacturing processes can be simplified and thereby costs can be reduced.

First claim

What is claimed is:

1. A shift register unit, comprising:
a first switching element that is switched on in response to an input signal so as to provide the input signal to a first node;
a second switching element that is switched on in response to a first clock signal so as to provide a first voltage to the first node;
a third switching element that is switched on in response to the first clock signal so as to provide the first voltage to a second node;
a fourth switching element that is switched on in response to a third clock signal so as to provide the input signal to the second node;
a fifth switching element that is switched on in response to a signal at the second node so as to input the first voltage to a third node;
a sixth switching element that is switched on in response to the first clock signal so as to provide a second voltage to the third node;
a seventh switching element that is switched on in response to a signal at the third node so as to provide the first voltage to an output signal terminal;
an eighth switching element that is switched on in response to a signal at the first node so as to provide a second clock signal to the output signal terminal;
a first capacitor coupled between the first voltage and the third node; and
a second capacitor coupled between the first node and the output signal terminal.

2. The shift register unit according to claim 1 , wherein the first to eighth switching elements are first to eight transistors, respectively.

3. The shift register unit according to claim 2 , wherein each of the first to eighth transistors has a first terminal, a second terminal and a control terminal;
the control terminal and the first terminal of the first transistor are coupled with the input signal, and the second terminal of the first transistor is coupled with the first node;
the control terminals of the second and third transistors are coupled with the first clock signal, the first terminals of the second and third transistors are coupled with the first voltage, the second terminal of the second transistor is coupled with the first node, and the second terminal of the third transistor is coupled with the second node;
the control terminal of the fourth transistor is coupled with the third clock signal, the first terminal of the fourth transistor is coupled with the input signal, and the second terminal of the fourth transistor is coupled with the second node;
the control terminal of the fifth transistor is coupled with the second node, the first terminal of the fifth transistor is coupled with the first voltage, and the second terminal of the fifth transistor is coupled with the third node;
the control terminal of the sixth transistor is coupled with the first clock signal, the first terminal of the sixth transistor is coupled with the second voltage, and the second terminal of the sixth transistor is coupled with the third node;
the control of the seventh transistor is coupled with the third node, the first terminal of the seventh transistor is coupled with the first voltage, and the second terminal of the seventh transistor is coupled with the output signal terminal; and
the control terminal of the eighth transistor is coupled with the first node, the first terminal of the eight transistor is coupled with the second clock signal, and the second terminal of the eighth transistor is coupled with the output signal terminal.

4. The shift register unit according to claim 3 , wherein the first to eighth transistors are N type transistors.

5. The shift register unit according to claim 3 , wherein the first to eighth transistors are P type transistors.

6. The shift register unit according to claim 5 , wherein the first clock signal is two thirds of a clock signal cycle ahead of the second clock signal in phase, and the second clock signal is two thirds of the clock signal cycle ahead of the third clock signal in phase.

7. The shift register unit according to claim 6 , wherein the first to third clock signals have a duty cycle of 1:3 which is a ratio between duration of a low level and the period of each clock signal.

8. The shift register unit according to claim 5 , wherein the first voltage is a high level voltage, and the second voltage is a low level voltage.

9. A gate driver circuit, comprising a plurality of shift register units, each of which comprises:
a first switching element that is switched on in response to an input signal so as to provide the input signal to a first node;
a second switching element that is switched on in response to a first clock signal so as to provide a first voltage to the first node;
a third switching element that is switched on in response to the first clock signal so as to provide the first voltage to a second node;
a fourth switching element that is switched on in response to a third clock signal so as to provide the input signal to the second node;
a fifth switching element that is switched on in response to a signal at the second node so as to input the first voltage to a third node;
a sixth switching element that is switched on in response to the first clock signal so as to provide a second voltage to the third node;
a seventh switching element that is switched on in response to a signal at the third node so as to provide the first voltage to an output signal terminal;
an eighth switching element that is switched on in response to a signal at the first node so as to provide a second clock signal to the output signal terminal;
a first capacitor coupled between the first voltage and the third node; and
a second capacitor coupled between the first node and the output signal terminal.

10. The gate driver circuit according to claim 9 , wherein the plurality of shift register units are cascaded; except the last stage of shift register unit, an output signal of each stage of shift register unit is coupled with an input signal terminal of a next stage of shift register unit, and an input signal of the first stage of shift register is input with a starting signal.

11. The gate driver circuit according to claim 10 , wherein the plurality of shift register units which are cascaded comprise at least a first shift register unit, a second shift register unit and a third shift register unit;
an output signal terminal of the first shift register unit is coupled with an input signal terminal of the second shift register unit; and
an output signal terminal of the second shift register unit is coupled with an input signal terminal of the third shift register unit.

12. The gate driver circuit according to claim 11 , further comprising:
a clock signal generation unit generating a first clock signal, a second clock signal and a third clock signal, wherein the first clock signal is two thirds of a clock signal cycle ahead of the second clock signal in phase, and the second clock signal is two thirds of the clock signal cycle ahead of the third clock signal in phase;
a first to third clock signals input to the first shift register unit are the first to third clock signals generated by the clock generation unit, respectively;
a first to third clock signals input to the second shift register unit are the third clock signal, the first clock signal and the second clock signal generated by the clock generation unit, respectively;
a first to third clock signals input to the third shift register unit are the second clock signal, the third clock signal and the first clock signal generated by the clock generation unit, respectively.

13. The gate driver circuit according to claim 9 , wherein the first to eighth switching elements are first to eight transistors, respectively.

Assignees

• Everdisplay Optronics Shanghai Ltd

Inventors

• Tseng Ying-Hsiang

Classifications

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title