Shift register unit, its driving method, gate driver circuit and display device

Patent metadata

Field	Value
Publication number	US-2017193961-A1
Application number	US-201615209250-A
Country	US
Kind code	A1
Filing date	Jul 13, 2016
Priority date	Jan 4, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

The present disclosure provides a shift register unit, its driving method, a gate driver circuit and a display device. The shift register unit includes a control module, a first output module and a second output module. The first output module is connected to a first signal end, a first node and an output end. The second output module is connected to the output end, a second node and a first clock signal end. The control module is connected to the first node, the second node, the first signal end, a second signal end, a second clock signal end, a third clock signal end, an input signal end and a resetting signal end, and configured to control potentials at the first node and the second node.

First claim

What is claimed is:

1 . A shift register unit, comprising a control module, a first output module and a second output module,
wherein the first output module is connected to a first signal end, a first node and an output end, and configured to input a first control signal from the first signal end to the output end under the control of the first node; the second output module is connected to the output end, a second node and a first clock signal end, and configured to input a first clock signal from the first clock signal end to the output end under the control of the second node; and the control module is connected to the first node, the second node, the first signal end, a second signal end, a second clock signal end, a third clock signal end, an input signal end and a resetting signal end, and configured to control potentials at the first node and the second node under the control of the first control signal from the first signal end, a second control signal from the second signal end, a second clock signal from the second clock signal end, a third clock signal from the third clock signal end, an input control signal from the input signal end and a resetting signal from the resetting signal end.

2 . The shift register unit according to claim 1 , wherein the control module comprises a first control sub-module, a second control sub-module, a resetting sub-module, a pull-up sub-module and a bleeder sub-module;
the first control sub-module is connected to the input signal end, the second clock signal end, the second signal end and a third node, and configured to input the second control signal from the second signal end to the third node under the control of the input control signal from the input signal end and the second clock signal from the second clock signal end; the second control sub-module is connected to the third clock signal end, the first signal end, the second signal end, the first node and the third node, and configured to input the second control signal from the second signal end to the first node and input the first control signal from the first signal end to the third node under the control of the third clock signal from the third clock signal end; the resetting sub-module is connected to the resetting signal end, the first signal end and the third node, and configured to input the first control signal from the first signal end to the third node under the control of the resetting signal from the resetting signal end; the pull-up sub-module is connected to the third node, the first signal end, the input signal end and the first node, and configured to input the first control signal from the first signal end to the first node under the control of the input control signal from the input signal end and the third node; and the bleeder sub-module is connected to the second signal end, the third node and the second node, and configured to input a potential at the third node to the second node under the control of the second control signal from the second signal end.

3 . The shift register unit according to claim 2 , wherein the first control sub-module comprises a first transistor and a second transistor;
a first electrode of the first transistor is connected to the second signal end, a second electrode of the first transistor is connected to a first electrode of the second transistor, and a third electrode of the first transistor is connected to the input signal end; and the first electrode of the second transistor is connected to the second electrode of the first transistor, a second electrode of the second transistor is connected to the third node, and a third electrode of the second transistor is connected to the second clock signal end.

4 . The shift register unit according to claim 2 , wherein the second control sub-module comprises a third transistor and a fourth transistor;
a first electrode of the third transistor is connected to the second signal end, a second electrode of the third transistor is connected to the first node and a third electrode of the fourth transistor, and a third electrode of the third transistor is connected to the third clock signal end; and a first electrode of the fourth transistor is connected to the first signal end, a second electrode of the fourth transistor is connected to the third node, and the third electrode of the fourth transistor is connected to the second electrode of the third transistor.

5 . The shift register unit according to claim 2 , wherein the resetting sub-module comprises a fifth transistor, a first electrode of which is connected to the first signal end, a second electrode of which is connected to the third node, and a third electrode of which is connected to the resetting signal end.

6 . The shift register unit according to claim 2 , wherein the pull-up sub-module comprises a sixth transistor and a seventh transistor;
a first electrode of the sixth transistor is connected to the first signal end, a second electrode of the sixth transistor is connected to the first node, and a third electrode of the sixth transistor is connected to the input signal end; and a first electrode of the seventh transistor is connected to the first signal end, a second electrode of the seventh transistor is connected to the first node, and a third electrode of the seventh transistor is connected to the third node.

7 . The shift register unit according to claim 2 , wherein the bleeder sub-module comprises an eighth transistor, a first electrode of which is connected to the third node, a second electrode of which is connected to the second node, and a third electrode of which is connected to the second signal end.

8 . The shift register unit according to claim 1 , wherein the first output module comprises a ninth transistor and a first capacitor;
a first electrode of the ninth transistor is connected to the first signal end, a second electrode of the ninth transistor is connected to the output end, and a third electrode of the ninth transistor is connected to the first node; and a first electrode of the first capacitor is connected to the first electrode of the ninth transistor, and a second electrode of the first capacitor is connected to the third electrode of the ninth transistor.

9 . The shift register unit according to claim 1 , wherein the second output module comprises a tenth transistor and a second capacitor;
a first electrode of the tenth transistor is connected to the first clock signal end, a second electrode of the tenth transistor is connected to the output end, and a third electrode of the tenth transistor is connected to the second node; and a first electrode of the second capacitor is connected to the second electrode of the tenth transistor and a second electrode of the second capacitor is connected to the third electrode of the tenth transistor.

10 . A method for driving the shift register unit according to claim 1 , the shift register unit comprising a first output module, a second output module and a control module, the method comprising steps of:
at a first stage, inputting, by a resetting signal end, a resetting signal at a second potential, and inputting, by the control module, a first control signal at a first potential from a first signal end to a second node; at a second stage, inputting, by a first clock signal end, a first clock signal at the first potential, inputting, by an input signal end, an input control signal at the second potential, inputting, by a second clock signal end, a second clock signal at the second potential, inputting, by the control module, the first control signal to a first node and inputting a second control signal at the second potential from a second signal end to the second node, and inp

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Wang Bo

Classifications

• G11C19/184 Primary

  with field-effect transistors, e.g. MOS-FET · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title