Shift register, driving method and gate driving circuit

Patent metadata

Field	Value
Publication number	US-2016189796-A1
Application number	US-201514860334-A
Country	US
Kind code	A1
Filing date	Sep 21, 2015
Priority date	Dec 30, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

Embodiments of the disclosure provide a shift register, a driving method and a gate driving circuit. In an embodiment, the shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first storage capacitor and a second storage capacitor. The shift register is driven by the cooperation of the respective transistors. In the case that the shift register is applied in the gate driving circuit to implement a line-by-line scanning, shift registers corresponding to two adjacent pixel rows are cascaded directly and no inverters are provided following the shift registers corresponding to the respective pixel rows, thereby decreasing the number of transistors in the gate driving circuit, reducing the layout area of the gate driving circuit, and being advantageous for narrowing the border.

First claim

What is claimed is:

1 . A shift register, comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first storage capacitor and a second storage capacitor; wherein
the first transistor is controlled by a voltage of a first node and is configured to transmit a first reference voltage to an output terminal of the shift register; the second transistor is controlled by a voltage of a second node and is configured to transmit a second reference voltage to the output terminal of the shift register, wherein the second reference voltage is lower than the first reference voltage; the third transistor is controlled by a first clock signal and is configured to transmit the first reference voltage to the first node; the fourth transistor is controlled by a voltage of a third node and is configured to transmit a second clock signal to the first node; the fifth transistor is controlled by the first clock signal and is configured to transmit a control signal to the second node; the sixth transistor is controlled by the first clock signal and is configured to transmit an input signal to a fourth node; the seventh transistor is controlled by a voltage of the fourth node and is configured to transmit the first reference voltage to the third node; the eighth transistor is controlled by the first clock signal and is configured to transmit a voltage of a fifth node to the third node; the ninth transistor is controlled by the second reference voltage and is configured to transmit the second reference voltage to the fifth node; the voltage of the fourth node is input to one polar plate of the first storage capacitor, and the first reference voltage is input to the other polar plate of the first storage capacitor; and the voltage of the second node is input to one polar plate of the second storage capacitor, and a voltage of the output terminal is input to the other polar plate of the second storage capacitor.

2 . The shift register of claim 1 , wherein a gate of the first transistor is electrically connected to the first node, the first reference voltage is input to a first electrode of the first transistor, and a second electrode of the first transistor is electrically connected to the output terminal;
a gate of the second transistor is electrically connected to the second node, a first electrode of the second transistor is electrically connected to the output terminal, and the second reference voltage is input to a second electrode of the second transistor; the first clock signal is input to a gate of the third transistor, the first reference voltage is input to a first electrode of the third transistor, and a second electrode of the third transistor is electrically connected to the first node; a gate of the fourth transistor is electrically connected to the third node, a first electrode of the fourth transistor is electrically connected to the first node, and the second clock signal is input to a second electrode of the fourth transistor; the first clock signal is input to a gate of the fifth transistor, a first electrode of the fifth transistor is electrically connected to the second node, and the control signal is input to a second electrode of the fifth transistor; the first clock signal is input to a gate of the sixth transistor, a first electrode of the sixth transistor is electrically connected to the fourth node, and the input signal is input to a second electrode of the sixth transistor; a gate of the seventh transistor is electrically connected to the fourth node, the first reference voltage is input to a first electrode of the seventh transistor, and a second electrode of the seventh transistor is electrically connected to the third node; the first clock signal is input to a gate of the eighth transistor, a first electrode of the eighth transistor is electrically connected to the third node, and a second electrode of the eighth transistor is electrically connected to the fifth node; the second reference voltage is input to a gate of the ninth transistor, a first electrode of the ninth transistor is electrically connected to the fifth node, and the second reference voltage is input to a second electrode of the ninth transistor; one polar plate of the first storage capacitor is electrically connected to the fourth node, and the other polar plate of the first storage capacitor is electrically connected to the first electrode of the seventh transistor; and one polar plate of the second storage capacitor is electrically connected to the second node, and the other polar plate of the second storage capacitor is electrically connected to the output terminal.

3 . The shift register of claim 1 , wherein the control signal is the first clock signal and the first clock signal is input to a second electrode of the fifth transistor.

4 . The shift register of claim 1 , wherein the control signal is the second reference voltage and the second reference voltage is input to a second electrode of the fifth transistor.

5 . The shift register of claim 2 , further comprising a tenth transistor; wherein
the tenth transistor is controlled by the voltage of the first node and is configured to transmit the first reference voltage to the second node.

6 . The shift register of claim 5 , wherein a gate of the tenth transistor is electrically connected to the first node, the first reference voltage is input to a first electrode of the tenth transistor, and a second electrode of the tenth transistor is electrically connected to the second node.

7 . The shift register of claim 6 , wherein the first clock signal and the second clock signal each comprises a plurality of first levels and a plurality of second levels, the first levels and the second levels are alternate, and the first level is the first reference voltage and the second level is the second reference voltage.

8 . The shift register of claim 2 , wherein a width to length ratio of a channel of the seventh transistor is greater than a width to length ratio of a channel of the ninth transistor, and a width to length ratio of a channel of the first transistor is greater than a width to length ratio of a channel of the second transistor.

9 . A driving method applied to a shift register, wherein the shift register comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first storage capacitor and a second storage capacitor; wherein
the first transistor is controlled by a voltage of a first node and is configured to transmit a first reference voltage to an output terminal of the shift register; the second transistor is controlled by a voltage of a second node and is configured to transmit a second reference voltage to the output terminal, wherein the second reference voltage is lower than the first reference voltage; the third transistor is controlled by a first clock signal and is configured to transmit the first reference voltage to the first node; the fourth transistor is controlled by a voltage of a third node and is configured to transmit a second clock signal to the first node; the fifth transistor is controlled by the first clock signal and is configured to transmit a control signal to the second node; the sixth transistor is controlled by the first clock signal and is configured to transmit an input signal to a fourth node; the seventh transistor is controlled by a voltage of the fourth node and is configured to transmit the first reference voltage to the third node; the eighth transistor is con

Assignees

• Shanghai Tianma Am Oled Co Ltd
• Tianma Micro Electronics Co Ltd

Inventors

• Wu Tong
• Qian Dong
• Zhang Tong

Classifications

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title