Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts

Patent metadata

Field	Value
Publication number	US-10014381-B2
Application number	US-201614987759-A
Country	US
Kind code	B2
Filing date	Jan 5, 2016
Priority date	Jun 1, 2010
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

First claim

We claim:

1. A semiconductor power device comprising:
gate trenches having recessed gate electrodes disposed below a top insulation plug protruding above a top surface of a semiconductor substrate wherein the top insulation plug in the gate trenches extending above and defining a substantially flat protuberance top surface recessed below the top insulation plug and extending between the gate trenches wherein the protuberance top surface protruding above the gate electrodes covered under the top insulation plug;
body regions disposed near the protuberance top surface encompassing source regions disposed below the protuberance top surface surrounded and defined by the top insulation plug extended above the gate trenches;
a silicide layer is formed over an entire area of the protuberance top surface for contacting both the source and body regions and the silicide layer is further disposed-on top of the recess gate electrode under the top insulation plug, wherein the silicide layer on top of the gate electrode is narrower than a width of the top insulation plug; and
a shield electrode disposed below the gate electrode in the gate trenches and an inter-electrode-dielectric separating the shield and gate electrodes whereby the device constituting a shield gate trench (SGT) MOSFET.

2. The device of claim 1 further comprising:
the silicide disposed on top of the recessed gate electrode under the top insulation plug having a narrower width than the recessed gate electrode.

3. The device of claim 1 wherein:
the silicide layer is composed of a salicided layer of one metal from a group of metals consisted of titanium, tungsten, nickel, cobalt, or palladium.

4. The device of claim 1 wherein:
the silicide layer disposed over an entire area of the protuberance top surface further laterally extends over the protuberance top surface to reach the sidewalls of the gate trenches.

5. The device of claim 1 further comprising:
a wide trench disposed on a terminal area of the power device having a greater width than the gate trenches wherein each of the gate trenches and the wide trench further includes a bottom shield electrode at the bottom of the wide trench and the gate trenches wherein the bottom shield electrodes are insulated from the recessed gate electrode by an inter-layer dielectric (ILD) layer and wherein the ILD dielectric layer filling in a middle portion of the wide trench with the recessed electrodes surrounding the ILD layer in the wide trench.

6. The device of claim 5 further comprising:
a shield electrode contact disposed in the wide trench penetrating the ILD layer occupying the middle portion of the wide trench and extends downward for contacting the bottom shield electrode.

7. The device of claim 6 further comprising:
a source metal covers over the wide trench in the terminal area and in contact with the shield electrode contact whereby the source metal is electrically connected to the bottom shielded electrodes.

8. The device of claim 5 wherein:
the recessed electrode disposed in the wide trench surrounding the ILD layer in the middle portion in the wide trench is electrically connected to at least one of the recessed gate electrodes.

9. The device of claim 8 wherein:
the wide trench further comprises a wide gate electrode protrusion wherein the protrusion comprising a gate bus connected to the gate electrodes disposed away from the termination area.

10. The device of claim 1 further comprising:
a shield electrode contacting trench comprising a shield electrode contact extending downwardly to contact the shield electrode.

11. The device of claim 1 further comprising:
an ESD structure comprising back to back source-gate diodes formed from alternating conductivity types in a trench electrode material.

12. The device of claim 1 further comprising:
Schottky diodes disposed on top of at least one of the semiconductor protuberances, said Schottky diodes also having silicide formed along the top of the semiconductor protuberances.

13. The device of claim 12 wherein:
the Schottky diodes have a junction barrier Schottky (JBS) pinching and a MOS (metal oxide semiconductor) pinching in a reverse blocking mode.

14. The device of claim 1 further comprising:
a top insulation layer covering over the top surface of the semiconductor substrate having a trenched source/body contact penetrates through the top insulation wherein trenched source/body contact contacting the silicide layer disposed on the protuberance top surface recessed below and defined by the top insulating plug.

15. The device of claim 1 wherein:
the source regions having a width ranging between 0.05 to 0.2 microns.

16. The device of claim 5 wherein:
the semiconductor substrate further includes a heavily doped bottom layer and a less heavily doped top layer, wherein the wide trench reaches the heavily doped bottom layer and the gate trenches having a shallower depth and downwardly extend only to the less heavily doped top layer.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Yilmaz Hamza
• Chen John
• Ng Daniel
• Li Wenjun

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L29/7827

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic

• H01L27/0255

  Electricity · mapped topic