Scanning drive circuit and organic light-emitting display

Patent metadata

Field	Value
Publication number	US-10013919-B2
Application number	US-201415107676-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Dec 30, 2013
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A scanning drive circuit is provided. Compared with traditional scan drive circuits, less clock signals and transistors are used. This can greatly enhance the reliability of the circuit, and reduce costs of design and manufacture. An organic light-emitting display based on the scanning drive circuit is also disclosed.

First claim

The invention claimed is:

1. A scanning drive circuit, comprising a first scan driver for sequentially outputting selection signals and a second scan driver for sequentially outputting transmission signals, wherein the first scan driver comprises a plurality of first cascade structures and the second scan driver comprises a plurality of second cascade structures, each cascade structure of the first cascade structures and/or the second cascade structures comprises:
a first transistor, comprising an input terminal directly connected to a scanning signal output terminal or a scanning signal input terminal of a precedent cascade structure, a gate terminal directly connected to a first clock end, and an output terminal;
a second transistor, comprising a gate terminal directly connected to the output terminal of the first transistor, an input terminal directly connected to a second clock end, and an output terminal directly connected to the scanning signal output terminal;
a third transistor, comprising an input terminal directly connected to a first level end, a gate terminal directly connected to the scanning signal output terminal, and an output terminal;
a fourth transistor, comprising an input terminal directly connected to the output terminal of the third transistor, a gate terminal directly connected to the first clock end, and an output terminal directly connected to a second level end;
a fifth transistor, comprising an input terminal directly connected to the first level end, a gate terminal directly connected to the output terminal of the third transistor, and an output terminal directly connected to the scanning signal output terminal;
a sixth transistor, comprising an input terminal directly connected to the first level end, a gate terminal directly connected to the scanning signal output terminal, and an output terminal;
a seventh transistor, comprising an input terminal directly connected to the output terminal of the sixth transistor, a gate terminal directly connected to the first clock end, and an output terminal directly connected to the second level end;
an eighth transistor, comprising an input terminal directly connected to the first level end, a gate terminal directly connected to the scanning signal output terminal, and an output terminal directly connected to a driving signal output terminal;
a ninth transistor, comprising an input terminal directly connected to the driving signal output terminal, a gate terminal directly connected to the output terminal of the sixth transistor, and an output terminal directly connected to a third level end; and
a first capacitor directly connected between the gate terminal and the output terminal of the second transistor.

2. The scanning drive circuit of claim 1 , wherein the signals received by the first clock end and the second clock end of each cascade structure of the first cascade structures and the second cascade structures are the same in frequency, the signal received by the second clock end is at low level when the signal received by the first clock end is at high level, and the signal received by the second clock end is at high level when the signal received by the first clock end is at low level.

3. The scanning drive circuit of claim 2 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are Thin Film Field Effect Transistors.

4. The scanning drive circuit of claim 1 , wherein a second capacitor is connected between the first level end and the gate terminal of the sixth transistor.

5. The scanning drive circuit of claim 1 , wherein a third capacitor is connected between the driving signal output terminal and the gate terminal of the ninth transistor.

6. The scanning drive circuit of claim 1 , wherein a third capacitor is connected between the second level end and the gate terminal of the ninth transistor.

7. The scanning drive circuit of claim 6 , wherein the third level end and the second level end are the same level end.

8. The scanning drive circuit of claim 6 , wherein the voltage value inputted from the third level end is smaller than the voltage value inputted from the second level end.

9. The scanning drive circuit of claim 6 , wherein the voltage inputted from the first level end is high level, and the voltages inputted from the second and third level ends are high level.

10. An organic light-emitting display, comprising a pixel circuit, a data driver and a timing controller, wherein the organic light-emitting display further comprises the scanning drive circuit of claim 1 , the timing controller supplies timing signals and high and low level signals to the first clock end, the second clock end, the scanning signal input terminal, the first level end, the second level end and the third level end of the scanning drive circuit, the driving signal output terminal of the scanning drive circuit is connected to the driving signal input terminal of the pixel circuit so as to output driving signals for driving the pixel circuit to operate.

Assignees

• Kunshan New Flat Panel Display Technology Ct Co Ltd
• Kunshan Govisionox Optoelectronics Co Ltd
• Kunshan New Flat Panel Display Technology Ct Co Ltd

Inventors

• Yang Nan
• Hu Siming
• Zhang Tingting
• Zhang Xiaobao
• Nagai Hajime
• Huang Xiuqi

Classifications

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title