Driver with separate power sources and display device using the same

Patent metadata

Field	Value
Publication number	US-9311856-B2
Application number	US-201113315548-A
Country	US
Kind code	B2
Filing date	Dec 9, 2011
Priority date	Jan 21, 2011
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A driver and a display device using the same may be provided. The driver, according to an exemplary embodiment includes at least one logic unit, receiving a plurality of clock signals and a plurality of input signals, to generate and sequentially transmit output signals to a plurality of pixel rows included in a display unit, and a buffer unit, receiving a plurality of control signals, to generate and simultaneously transmit the output signals of a same waveform to a plurality of pixels included in the display unit, wherein the at least one logic unit is supplied with a logic power source voltage, and the buffer unit is supplied with a buffer power source voltage, the buffer power source voltage being different from the logic power source voltage.

First claim

What is claimed is:

1. A driver, comprising:
at least one logic circuit to receive a plurality of clock signals and a plurality of input signals to generate and sequentially transmit first and second output signals to a plurality of pixel rows included in a display; and
a buffer, receiving the first output signal, the second output signal, a first control signal, and a second control signal, to generate and transmit a light emission control signal of a same waveform to a plurality of pixels included in the display, wherein the at least one logic circuit includes a first logic circuit receiving the plurality of clock signals and a first input signal to generate the first output signal, and a second logic circuit receiving the plurality of clock signals and a second input signal to generate the second output signal,
wherein the at least one logic circuit is supplied with a logic power source voltage, and the buffer is supplied with a buffer power source voltage,
wherein the buffer power source voltage is different from the logic power source voltage, and
wherein in a case of a simultaneous driving mode in which the light emission control signal is simultaneously output with a same waveform, the first input signal and the second input signal are transmitted with a gate-off voltage level to the first logic circuit and the second logic circuit, such that the first logic circuit and the second logic circuit, respectively, are not operated.

2. The driver as claimed in claim 1 , wherein: the logic power source voltage includes a first logic power source voltage of a predetermined voltage level and a second logic power source voltage of a lower voltage level than the first logic power source voltage.

3. The driver as claimed in claim 1 , wherein: the buffer power source voltage includes a first buffer power source voltage of a predetermined voltage level and a second buffer power source voltage of a lower voltage level than the first buffer power source voltage.

4. The driver as claimed in claim 1 , wherein:
in a case of a simultaneous driving mode in which the light emission control signal is simultaneously output with a same waveform, a pulse width of the light emission control signal is determined by a period difference between a time that the first control signal is transmitted with a pulse of a gate-on voltage and the time that the second control signal is transmitted with the pulse of the gate-on voltage level.

5. The driver as claimed in claim 1 , wherein:
in a case of a sequential driving mode in which the light emission control signal is sequentially output to a plurality of pixel rows of the display, the pulse width of the light emission control signal is determined by a period difference between a time that the first input signal is transmitted to the first logic circuit with a gate-on voltage level and a time that the second input signal is transmitted to the second logic circuit with the gate-on voltage level.

6. The driver as claimed in claim 5 , wherein:
a time that a phase of the light emission control signal is changed into a gate-off voltage level is synchronized with a transmission time of a first low level pulse, the first low level pulse being from the plurality of clock signals transmitted to the first logic circuit when the first input signal is transmitted with the gate-on voltage level, and
a time that the phase of the light emission control signal is changed into the gate-on voltage level is synchronized with a transmission time of a second low level pulse, the second low level pulse being from the plurality of clock signals transmitted to the second logic circuit when the second input signal is transmitted with the gate-on voltage level.

7. The driver as claimed in claim 1 , wherein:
the first logic circuit includes:
a first switch, switchably operated by a first clock signal among the plurality of clock signals and transmitting a first voltage according to the first input signal to a first node,
a second switch switchably operated by the first input signal and transmitting the first logic power source voltage to a second node,
a third switch switchably operated corresponding to the first voltage transmitted to the first node and transmitting a second voltage according to a second clock signal among the plurality of clock signals as a first output voltage of the first output signal,
a fourth switch switchably operated corresponding to the first logic power source voltage transmitted to the second node and transmitting the first logic power source voltage as a first output voltage of the first output signal,
a first capacitor storing the voltage transmitted to the first node, and
a second capacitor storing the voltage transmitted to the second node.

8. The driver as claimed in claim 7 , wherein the first logic circuit includes:
a fifth switch switchably operated by a third clock signal among the plurality of clock signals and transmitting a second logic power source voltage having a lower level than the first logic power source voltage, to the second node, and
at least one sixth switch switchably operated by the second logic power source voltage transmitted to the second node and transmitting the first logic power source voltage to the first node.

9. The driver as claimed in claim 1 , wherein:
the second logic circuit includes:
a seventh switch switchably operated by a third clock signal among the plurality of clock signals and transmitting a third voltage according to the second input signal to a third node,
an eighth switch switchably operated by the second input signal and transmitting the first logic power source voltage to a fourth node,
a ninth switch switchably operated corresponding to the third voltage transmitted to the third node and transmitting a fourth voltage according to a first clock signal among the plurality of clock signals as a second output voltage level of the second output signal,
a tenth switch switchably operated corresponding to the first logic power source voltage transmitted to the fourth node and transmitting the first logic power source voltage as the second output voltage level of the second output signal,
a third capacitor storing the voltage transmitted to the third node; and
a fourth capacitor storing the voltage transmitted to the fourth node.

10. The driver as claimed in claim 9 , wherein:
the second logic circuit includes:
an eleventh switch switchably operated by a second clock signal, among the plurality of clock signals, and transmitting the second logic power source voltage, the second logic power source voltage having a lower level than the first logic power source voltage, to the fourth node; and
at least one twelfth switch switchably operated by the second logic power source voltage transmitted to the fourth node and transmitting the first logic power source voltage to the third node.

11. The driver as claimed in claim 1 , wherein:
the buffer includes:
at least one thirteenth switch switchably operated by the first output signal and transmitting a first buffer power source voltage to a fifth node,
at least one fourteenth switch switchably operated by the first output signal and transmitting a second buffer power source voltage, the second buffer power source voltage having a lower level than the first buffer power source voltage to a sixth node,
at least one fifteenth switch switchably operated by the second output signal and transmitting the second buffer power source voltage to the fifth node,
at least one sixteenth switch switchably operated by a first control signal and transmitting the first buffer power source voltage to the fifth node,
at least one seventeenth switch switchably operated

Assignees

• Park Dong-Wook
• Kang Ki-Nyeng
• Kim Keum-Nam
• Samsung Display Co Ltd

Inventors

• Park Dong-Wook
• Kang Ki-Nyeng
• Kim Keum-Nam

Classifications

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G09G2320/064

  by time modulation of the brightness of the illumination source · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title