Fingerprinting of redundant threads using compiler-inserted transformation code

Patent metadata

Field	Value
Publication number	US-10013240-B2
Application number	US-201615188304-A
Country	US
Kind code	B2
Filing date	Jun 21, 2016
Priority date	Jun 21, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A first processing element is configured to execute a first thread and one or more second processing elements are configured to execute one or more second threads that are redundant to the first thread. The first thread and the one or more second threads are to selectively bypass one or more comparisons of results of operations performed by the first thread and the one or more second threads depending on whether an event trigger for the comparison has occurred a configurable number of times since a previous comparison of previously encoded values of the results. In some cases the comparison can be performed based on hashed (or encoded) values of the results of a current operation and one or more previous operations.

First claim

What is claimed is:

1. A method comprising:
executing redundant threads on corresponding processing elements;
generating encoded values of results of operations performed by the redundant threads by hashing the results with at least one of a previous encoded value and an initial value, wherein the encoded values are generated in response to the redundant threads executing event triggers for comparisons of the results; and
selectively bypassing at least one comparison of the encoded values depending on whether the event trigger has occurred a configurable number of times since a previous comparison of previously encoded values of the results.

2. The method of claim 1 , wherein the configurable number is greater than one.

3. The method of claim 1 , wherein the event trigger is a store instruction executed by the redundant threads to store the results to a memory.

4. The method of claim 1 , wherein executing the redundant threads on the corresponding processing elements comprises concurrently executing the redundant threads on the corresponding processing elements.

5. The method of claim 1 , further comprising:
modifying program code that is to be executed by the redundant threads by inserting code during compilation to generate a lookup table of code values that are used to hash the results.

6. The method of claim 5 , wherein modifying the program code during compilation further comprises initializing a counter for each of the redundant threads, wherein each counter is incremented in response to the redundant threads executing the event trigger, and wherein the value of the counter is compared to the configurable number to determine whether to selectively bypass the at least one comparison.

7. The method of claim 6 , wherein modifying the program code during compilation further comprises inserting code to hash the results to generate the encoded values, to compare the value of the counter to the configurable number to determine whether to selectively bypass the at least one comparison, and to share-and-compare the encoded values between the redundant threads in response to determining that the event trigger for the comparison has occurred the configurable number of times.

8. The method of claim 7 , wherein modifying the program code during compilation further comprises inserting code to determine whether an outstanding share-and-compare operation is to be performed before the redundant threads exit the program code.

9. An apparatus comprising:
a first processing element to execute a first thread; and
at least one second processing element to execute at least one second thread that is redundant to the first thread, wherein the first processing element and the at least one second processing element encoded values of results of operations performed by the first thread and the at least one second thread, respectively, by hashing the results with at least one of a previous encoded value and an initial value, wherein the encoded values are generated in response to the first thread and the at least one second thread executing event triggers for comparisons of the results, and wherein the first processing element and the at least one second processing element are to selectively bypass at least one comparison of the encoded values depending on whether the event trigger has occurred a configurable number of times since a previous comparison of previously encoded values of the results.

10. The apparatus of claim 9 , wherein the configurable number is greater than one.

11. The apparatus of claim 9 , wherein the event trigger is a store instruction executed by the redundant threads to store the results.

12. The apparatus of claim 9 , wherein the first thread and the at least one second thread are executed concurrently by the first processing element and the at least one second processing element respectively.

13. The apparatus of claim 9 , further comprising:
a plurality of processing elements that include the first processing element and the at least one second processing element, wherein the plurality of processing elements implement a compiler configured to modify program code that is to be executed by the first thread and the at least one second thread by inserting code during compilation to generate a lookup table of code values that are used to hash the results to generate the encoded values.

14. The apparatus of claim 13 , further comprising:
a memory configured to implement counters for the first thread and the at least one second thread, wherein the compiler is configured to initialize the counters, wherein the first thread or the at least one second thread increment the corresponding counter in response to executing the event trigger, and wherein the values of the counters are compared to the configurable number to determine whether to selectively bypass the at least one comparison.

15. The apparatus of claim 14 , wherein the compiler is configured to insert code to hash the results, to compare the values of the counters to the configurable number to determine whether to selectively bypass the at least one comparison, and to share-and-compare the encoded values between the first thread and the at least one second thread in response to determining that the event trigger for the comparison has occurred the configurable number of times.

16. The apparatus of claim 15 , wherein the compiler is configured to insert code to determine whether an outstanding share-and-compare operation is to be performed before the first thread and the at least one second thread exit the program code.

17. A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor element to:
execute redundant threads on corresponding processing elements;
generate encoded values of results of operations performed by the redundant threads by hashing the results with at least one of a previous encoded value and an initial value, wherein the encoded values are generated in response to the redundant threads executing event triggers for comparisons of the results; and
selectively bypass at least one comparison of the encoded values depending on whether the event trigger has occurred a configurable number of times since a previous comparison of previously encoded values of the results.

18. The non-transitory computer readable medium of claim 17 , wherein the at least one processor element is to initialize a counter for each of the redundant threads, wherein each counter is incremented in response to the redundant threads executing the event trigger, and wherein the value of the counter is compared to the configurable number to determine whether to selectively bypass the at least one comparison.

19. The non-transitory computer readable medium of claim 18 , wherein the at least one processor element is to insert code to hash the results with at least one of a previous encoded value and an initial value to generate encoded values, to compare the value of the counter to the configurable number to determine whether to selectively bypass the at least one comparison, and to share-and-compare the encoded values between the redundant threads in response to determining that the event trigger for the comparison has occurred the configurable number of times.

20. The non-transitory computer readable medium of claim 19 , wherein the at least one processor element is to insert code to determine whether an outstanding share-and-compare operation is to be performed before the redundant threa

Assignees

• Advanced Micro Devices Inc

Inventors

• Lowell Daniel I

Classifications

• G06F11/1494

  N-modular type · CPC title

• G06F11/1633

  using mutual exchange of the output between the redundant processing components · CPC title

• G06F2201/83

  the solution involving signatures · CPC title

• G06F8/41

  Compilation · CPC title

• G06F2201/805

  Real-time · CPC title