Instruction to cancel outstanding cache prefetches

Patent metadata

Field	Value
Publication number	US-9535696-B1
Application number	US-201614987411-A
Country	US
Kind code	B1
Filing date	Jan 4, 2016
Priority date	Jan 4, 2016
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Techniques relate to handling outstanding cache miss prefetches. A processor pipeline recognizes that a prefetch canceling instruction is being executed. In response to recognizing that the prefetch canceling instruction is being executed, all outstanding prefetches are evaluated according to a criterion as set forth by the prefetch canceling instruction in order to select qualified prefetches. In response to evaluating, a cache subsystem is communicated with to cause canceling of the qualified prefetches that fit the criterion. In response to successful canceling of the qualified prefetches, a local cache is prevented from being updated from the qualified prefetches.

First claim

What is claimed is:

1. A computer implemented method for handling outstanding cache miss prefetches, the method comprising:
recognizing by a processor pipeline that a prefetch canceling instruction is being executed, wherein the prefetch canceling instruction has been inserted immediately after or before a transaction in which the transaction is known in advance to have a likelihood of utilizing a predefined amount of hardware transactional support structures;
in response to recognizing that the prefetch canceling instruction is being executed, evaluating all outstanding prefetches according to a criterion as set forth by the prefetch canceling instruction in order to select qualified prefetches;
in response to evaluating, communicating with a cache subsystem to cause canceling of the qualified prefetches that fit the criterion, wherein the prefetch canceling instruction cancels the qualified prefetches that are not linked with any pending instructions; and
in response to successful canceling of the qualified prefetches, preventing a local cache from being updated from the qualified prefetches.

2. The method of claim 1 , wherein the criterion comprises canceling outstanding cache miss requests that are not required by any outstanding instructions.

3. The method of claim 1 , wherein the criterion comprises cancelling outstanding cache miss requests that are generated by a pattern based prefetcher engine.

4. The method of claim 1 , wherein the criterion indicates no qualification is required such that the all outstanding prefetches are to be canceled.

5. The method of claim 1 , wherein the prefetch cancelling instruction is configured to cause an additional action to stop a pattern based prefetcher engine until a context switch or until a pre-set time duration expires.

6. The method of claim 5 , wherein the pattern based prefetcher engine previously stopped is to resume operation when a transaction completes.

7. The method of claim 1 , wherein the prefetch cancel instruction is configured to specify a beginning of a transaction, where the transaction is a group of instructions that operate in an atomic manner.

8. A computer program product for handling outstanding cache miss prefetches, the computer program product comprising:
a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform steps comprising:
recognizing by a processor pipeline that a prefetch canceling instruction is being executed, wherein the prefetch canceling instruction has been inserted immediately after or before a transaction in which the transaction is known in advance to have a likelihood of utilizing a predefined amount of hardware transactional support structures;
in response to recognizing that the prefetch canceling instruction is being executed, evaluating all outstanding prefetches according to a criterion as set forth by the prefetch canceling instruction in order to select qualified prefetches;
in response to evaluating, communicating with a cache subsystem to cause canceling of the qualified prefetches that fit the criterion, wherein the prefetch canceling instruction cancels the qualified prefetches that are not linked with any pending instructions; and
in response to successful canceling of the qualified prefetches, preventing a local cache from being updated from the qualified prefetches.

9. The computer program product of claim 8 , wherein the criterion comprises canceling outstanding cache miss requests that are not required by any outstanding instructions.

10. The computer program product of claim 8 , wherein the criterion comprises cancelling outstanding cache miss requests that are generated by a pattern based prefetcher engine.

11. The computer program product of claim 9 , wherein the criterion indicates no qualification is required such that the all outstanding prefetches are to be canceled.

12. The computer program product of claim 9 , wherein the prefetch cancelling instruction is configured to cause an additional action to stop a pattern based prefetcher engine until a context switch or until a pre-set time duration expires.

13. The computer program product of claim 12 , wherein the pattern based prefetcher engine previously stopped is to resume operation when a transaction completes.

14. The computer program product of claim 9 , wherein the prefetch cancel instruction is configured to specify a beginning of a transaction, where the transaction is a group of instructions that operate in an atomic manner.

15. A computer system for handling outstanding cache miss prefetches, the system comprising:
a memory; and
a processor, communicatively coupled to the memory, the computer system configured to perform steps comprising:
recognizing by a processor pipeline that a prefetch canceling instruction is being executed, wherein the prefetch canceling instruction has been inserted immediately after or before a transaction in which the transaction is known in advance to have a likelihood of utilizing a predefined amount of hardware transactional support structures;
in response to recognizing that the prefetch canceling instruction is being executed, evaluating all outstanding prefetches according to a criterion as set forth by the prefetch canceling instruction in order to select qualified prefetches;
in response to evaluating, communicating with a cache subsystem to cause canceling of the qualified prefetches that fit the criterion, wherein the prefetch canceling instruction cancels the qualified prefetches that are not linked with any pending instructions; and
in response to successful canceling of the qualified prefetches, preventing a local cache from being updated from the qualified prefetches.

16. The computer system of claim 15 , wherein the criterion comprises canceling outstanding cache miss requests that are not required by any outstanding instructions.

17. The computer system of claim 15 , wherein the criterion comprises cancelling outstanding cache miss requests that are generated by a pattern based prefetcher engine.

18. The computer system of claim 15 , wherein the criterion indicates no qualification is required such that the all outstanding prefetches are to be canceled.

19. The computer system of claim 15 , wherein the prefetch cancelling instruction is configured to cause an additional action to stop a pattern based prefetcher engine until a context switch or until a pre-set time duration expires.

20. The computer system of claim 19 , wherein the pattern based prefetcher engine previously stopped is to resume operation when a transaction completes.

Assignees

• IBM

Inventors

• Gschwind Michael Karl
• Michael Maged M
• Salapura Valentina
• Schwarz Eric M
• Shum Chung-Lung K

Classifications

• G06F2212/6022

  Using a prefetch buffer or dedicated prefetch cache · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F2212/1021

  Hit rate improvement · CPC title