Solar cell powered integrated circuit device and method therefor

Patent metadata

Field	Value
Publication number	US-10008447-B2
Application number	US-201514718168-A
Country	US
Kind code	B2
Filing date	May 21, 2015
Priority date	May 21, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A semiconductor device includes a circuitry die and a solar cell die. The circuitry die includes a plurality of interconnect layers on a front side of the circuitry die, a metallization layer on a back side of the circuitry die, and at least one TSV (through substrate via) that makes an electrical connection between a last metal interconnect layer on the front side of the circuitry die and the metallization layer on the back side of the circuitry die. The solar cell die is configured to power the circuitry die. The solar cell die includes a transparent contact on a front side of the solar cell die. A back side of the solar cell die is attached to the back side of the circuitry die and makes electrical contact with the metallization layer on the back side of the circuitry die.

First claim

What is claimed is:

1. A semiconductor device comprising:
a circuitry die comprising:
a plurality of interconnect layers on a front side of the circuitry die,
a metallization layer on a back side of the circuitry die, and
at least one TSV (through silicon via) filled with a metal plug that contacts and extends from a portion of a last metal interconnect layer on the front side of the circuitry die to the metallization layer on the back side of the circuitry die, wherein
the at least one TSV is surrounded by a non-conductive liner that insulates the TSV from the plurality of interconnect layers except the last metal interconnect layer; and

a solar cell die configured to power the circuitry die, the solar cell die comprising:
a transparent contact on a front side of the solar cell die, wherein
a back side of the solar cell die is attached to the back side of the circuitry die and makes electrical contact with the metallization layer on the back side of the circuitry die.

2. The semiconductor device of claim 1 , further comprising:
wiring external to the circuitry die between the transparent contact of the solar cell die and a contact on the front side of the circuitry die.

3. The semiconductor device of claim 1 , further comprising:
at least one power TSV filled with a metal plug that contacts and extends from another portion of the last metal interconnect layer on the front side of the circuitry die to the transparent contact on the front side of the solar cell die.

4. The semiconductor device of claim 1 , further comprising:
a package having a window, wherein
the circuitry die is attached to an interior surface of the package, and
the solar cell die is exposed to light through the window.

5. The semiconductor device of claim 4 , wherein
the package has a surface area smaller than one square centimeter.

6. The semiconductor device of claim 1 , wherein
the at least one TSV makes electrical contact with at least one of the plurality of interconnect layers.

7. The semiconductor device of claim 1 , wherein
the circuitry die is less than 100 microns thick.

8. The semiconductor device of claim 1 , wherein
the circuitry die further comprises an energy storage capacitor.

9. The semiconductor device of claim 1 , wherein
the circuitry die further comprises antenna circuitry.

10. The semiconductor device of claim 1 , wherein
the circuitry die further comprises data collection circuitry.

11. The semiconductor device of claim 1 , wherein
the circuitry die further comprises external connections configured to be connected to external data collection circuitry.

12. The semiconductor device of claim 1 , wherein
the solar cell die comprises at least one of a group including crystalline silicon solar cells, monocrystalline silicon solar cells, amorphous silicon solar cells, thin film solar cells, single-junction solar cells, and multi-junction solar cells.

13. A semiconductor device comprising:
a circuitry die comprising:
a plurality of interconnect layers on a front side of the circuitry die, and
a metallization layer on a back side of the circuitry die; and

a solar cell die configured to power the circuitry die, the solar cell die comprising:
a transparent contact on a front side of the solar cell die, wherein
a back side of the solar cell die is attached to the back side of the circuitry die and makes electrical contact with the metallization layer on the back side of the circuitry die; and

at least one power TSV (through silicon via) filled with a metal plug that contacts and extends from a portion of a last metal interconnect layer on the front side of the circuitry die to the transparent contact on the front side of the solar cell die, wherein
the at least one power TSV is surrounded by a non-conductive liner that insulates the at least one power TSV from the plurality of interconnect layers except the last metal interconnect layer.

14. The semiconductor device of claim 13 , wherein
the semiconductor device has a surface area smaller than one square centimeter.

15. The semiconductor device of claim 13 , further comprising:
a package having a window, wherein
the circuitry die is attached to an interior surface of the package, and
the solar cell die is exposed to light through the window.

16. The semiconductor device of claim 13 , wherein the circuitry die further comprises:
at least one ground TSV filled with a metal plug that contacts and extends from another portion of the last metal interconnect layer on the front side of the circuitry die to the metallization layer on the back side of the circuitry die.

17. A semiconductor device comprising:
a circuitry wafer comprising:
a plurality of interconnect layers on a front side of the circuitry wafer,
a metallization layer on a back side of the circuitry wafer, and
a plurality of TSVs (through silicon vias) each filled with a metal plug that contacts and extends from a respective portion of a last metal interconnect layer on the front side of the circuitry wafer to the metallization layer on the back side of the circuitry wafer; and

a solar cell wafer comprising:
a transparent contact on a front side of the solar cell wafer, wherein
a back side of the solar cell wafer is attached to the back side of the circuitry wafer and makes electrical contact with the metallization layer on the back side of the circuitry wafer.

18. The semiconductor device of claim 17 , further comprising:
a plurality of power TSVs each filled with a metal plug that contacts and extends from another respective portion of the last metal interconnect layer on the front side of the circuitry wafer to the transparent contact on the front side of the solar cell wafer.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Reber Douglas M
• Shroff Mehul D

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W90/00

  Package configurations · CPC title