Gate structure cut after formation of epitaxial active regions

Patent metadata

Field	Value
Publication number	US-10008415-B2
Application number	US-201715419346-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Jan 24, 2014
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a plurality of semiconductor material portions on a substrate;
forming a contiguous gate structure and a gate spacer that straddle said plurality of semiconductor material portions;
forming a plurality of epitaxial active regions on physically exposed surfaces of said plurality of semiconductor material portions; and
cutting said contiguous gate structure and said gate spacer into a plurality of assemblies, each of said plurality of assemblies includes a gate structure and a pair of gate spacer portions that are disjoined from each other, wherein said cutting concurrently removes at least one portion of the plurality of epitaxial active regions and provides a cut epitaxial active region portion that has a sidewall that is within a same vertical plane as a sidewall of one of said assemblies.

2. The method of claim 1 , wherein each of said pair of gate spacer portions contacts a widthwise sidewall of said gate structure and is laterally spaced from each other by said gate structure along said lengthwise direction.

3. The method of claim 1 , further comprising forming at least one dielectric liner, wherein each of said at least one dielectric liner contacts lengthwise sidewalls and widthwise sidewalls of one of said plurality of assemblies, and laterally surrounds one of said plurality of semiconductor material portions.

4. The method of claim 3 , wherein said at least one dielectric liner is a plurality of dielectric liners.

5. The method of claim 4 , wherein said plurality of dielectric liners is formed by deposition of a contiguous dielectric material layer and an anisotropic etch that removes horizontal portions of said contiguous dielectric material layer, and top surfaces of said plurality of epitaxial active regions are physically exposed upon formation of said plurality of dielectric liners.

6. The method of claim 4 , further comprising forming a plurality of metal semiconductor alloy regions on top surfaces of said semiconductor material portions, wherein a periphery one of said plurality of metal semiconductor alloy regions is laterally bounded by a periphery of an opening within one of said plurality of dielectric liners.

7. The method of claim 3 , wherein said at least one dielectric liner is a contiguous dielectric liner that contacts top surfaces of said plurality of epitaxial active regions.

8. The method of claim 3 , wherein said at least one dielectric liner does not contact any surface of said plurality of semiconductor material portions, and is laterally spaced from said plurality of semiconductor material portions by one of said gate spacer portions and said plurality of epitaxial active regions.

9. The method of claim 1 , wherein each semiconductor material portion is a semiconductor fin, and said substrate is an insulator layer of a semiconductor-on-insulator substrate.

10. The method of claim 1 , wherein each semiconductor material portion is a semiconductor fin, and said substrate is a semiconductor material.

11. The method of claim 1 , further comprising forming a source region and a drain region on opposite sides of the contiguous gate structure and within a physically exposed portion of each semiconductor material portion, wherein said forming said source region and said drain region is performed prior to said forming said plurality of epitaxial active regions.

12. The method of claim 1 , wherein said forming said plurality of epitaxial active regions comprises a selective epitaxial growth process.

13. The method of claim 1 , wherein said cutting said contiguous gate structure and said gate spacer comprises:
forming a mask layer over said semiconductor material portions, said contiguous gate structure, said gate spacer and said epitaxial active regions;
forming openings in said mask, wherein said openings are located in regions including interfaces between the epitaxial active regions and said gate spacer; and
removing physically exposed portions of the contiguous gate structure, said gate spacer and said epitaxial active regions.

14. The method of claim 13 , wherein said removing comprises an anisotropic etch.

15. The method of claim 13 , wherein an edge of at least one of said openings overlies said contiguous gate structure, said gate spacer and at least four of said plurality of epitaxial active regions.

16. The method of claim 13 , wherein each opening has a shape of a rectangle having two pairs of parallel edges.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cai Xiuyu
• Cheng Kangguo
• Faltermeier Johnathan E
• Khakifirooz Ali
• Standaert Theodorus E
• Xie Ruilong

Classifications

• H10P50/283

  by chemical means · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/41783

  Electricity · mapped topic

• H01L21/823437 Primary

  Electricity · mapped topic