Gate structure cut after formation of epitaxial active regions

Patent metadata

Field	Value
Publication number	US-9559009-B2
Application number	US-201514876212-A
Country	US
Kind code	B2
Filing date	Oct 6, 2015
Priority date	Jan 24, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a plurality of semiconductor material portions on a substrate;
forming a contiguous gate structure and a gate spacer that straddle said plurality of semiconductor material portions;
forming a plurality of epitaxial active regions on physically exposed surfaces of said plurality of semiconductor material portions; and
cutting said contiguous gate structure and said gate spacer into a plurality of assemblies, each of said plurality of assemblies including a gate structure and a pair of gate spacer portions that are disjoined from each other, and wherein at least one portion of said plurality of epitaxial active regions is removed concurrently with said cutting of said contiguous gate structure.

2. The method of claim 1 , wherein each of said pair of gate spacer portions contacts a widthwise sidewall of said gate structure and is laterally spaced from each other by said gate structure along said lengthwise direction.

3. The method of claim 1 , further comprising applying and patterning a photoresist layer over said contiguous gate structure, said gate spacer, and said plurality of epitaxial active regions, wherein an edge of an opening in said photoresist layer overlies said contiguous gate structure, said gate spacer, and at least four of said plurality of epitaxial active regions.

4. The method of claim 3 , wherein said gate structure and said pair of gate spacer portions have sidewalls that are located within a same vertical plane.

5. The method of claim 1 , further comprising forming at least one dielectric liner, wherein each of said at least one dielectric liner contacts lengthwise sidewalls and widthwise sidewalls of one of said plurality of assemblies, and laterally surrounds one of said plurality of semiconductor material portions.

6. The method of claim 5 , wherein said at least one dielectric liner is a plurality of dielectric liners, and is formed by deposition of a contiguous dielectric material layer and an anisotropic etch that removes horizontal portions of said contiguous dielectric material layer, and top surfaces of said plurality of epitaxial active regions are physically exposed upon formation of said plurality of dielectric liners.

7. The method of claim 6 , further comprising forming a plurality of metal semiconductor alloy regions on top surfaces of said semiconductor material portions, wherein a periphery one of said plurality of metal semiconductor alloy regions is laterally bounded by a periphery of an opening within one of said plurality of dielectric liners.

8. The method of claim 5 , wherein said at least one dielectric liner is a contiguous dielectric liner that contacts top surfaces of said plurality of epitaxial active regions.

9. The method of claim 5 , wherein said at least one dielectric is laterally spaced from said plurality of semiconductor material portions by one of said gate spacer portions and said plurality of epitaxial active regions.

10. A method of forming a semiconductor structure comprising:
forming a plurality of semiconductor material portions on a substrate;
forming a contiguous gate structure and a gate spacer that straddle said plurality of semiconductor material portions;
forming a plurality of epitaxial active regions on physically exposed surfaces of said plurality of semiconductor material portions;
applying and patterning a photoresist layer over said contiguous gate structure, said gate spacer, and said plurality of epitaxial active regions, wherein an edge of an opening in said photoresist layer overlies said contiguous gate structure, said gate spacer, and at least four of said plurality of epitaxial active regions; and
cutting said contiguous gate structure and said gate spacer into a plurality of assemblies, each of said plurality of assemblies including a gate structure and a pair of gate spacer portions that are disjoined from each other.

Assignees

• IBM
• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Cai Xiuyu
• Cheng Kangguo
• Faltermeier Johnathan E
• Khakifirooz Ali
• Standaert Theodorus E
• Xie Ruilong

Classifications

• H10P50/283

  by chemical means · CPC title

• H01L21/823431

  Electricity · mapped topic

• H01L29/665

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H01L21/823468

  Electricity · mapped topic