Memristive cross-bar array for determining a dot product

Patent metadata

Field	Value
Publication number	US-10008264-B2
Application number	US-201415521542-A
Country	US
Kind code	B2
Filing date	Oct 23, 2014
Priority date	Oct 23, 2014
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.

First claim

What is claimed is:

1. A memristive cross-bar array for determining a dot product, comprising:
a plurality of row lines;
a plurality of column lines intersecting the row lines to form respective junctions;
a plurality of resistive memory elements coupled between the row lines and the column lines at the junctions,
the row lines to provide programming signals to the resistive memory elements, the programming signals defining matrix values within a matrix of the resistive memory elements; and
the row lines to provide vector signals at the resistive memory elements, the vector signals defining vector values to be applied to the resistive memory elements;

a current collection line to collect all currents output from the resistive memory elements through the respective column lines, the collected currents equaling a dot product of the matrix values and the vector values; and
circuits connected to the row lines to apply a reference voltage to shift an operation region of the memristive cross-bar array based on the reference voltage.

2. The memristive cross-bar array of claim 1 , wherein the shift of the operation region is based on a ratio of a voltage of an input voltage into the circuits and a voltage of the reference voltage input into the circuits.

3. The memristive cross-bar array of claim 2 , wherein the ratio comprises voltages such that the reference voltage is equal to a maximum voltage of the input voltage divided by two.

4. The memristive cross-bar array of claim 1 , wherein the circuits comprise negative feedback operational amplifiers.

5. The memristive cross-bar array of claim 1 , wherein a calculation of all sums and products of the dot product are performed simultaneously by the memristive cross-bar array.

6. The memristive cross-bar array of claim 1 , wherein the memristive cross-bar array is used as an accelerator in connection with a computer program such that an output of the memristive cross-bar array is coupled to a processing device as input for the computer program.

7. The memristive cross-bar array of claim 1 , wherein a first programming signal of the programming signals is provided over a first row line of the row lines, and a first vector signal of the vector signals is provided over the first row line, wherein the first programming signal is set to a voltage to change a resistance of a first resistive memory element of the memristive cross-bar array, and the first vector signal is set to a voltage lower than the voltage of the first programming signal such that the first vector signal does not change the resistance of the first resistive memory element.

8. The memristive cross-bar array of claim 4 , wherein each respective negative feedback operational amplifier of the negative feedback operational amplifiers has a first input connected to a respective row line of the row lines, and a second input connected to the reference voltage.

9. The memristive cross-bar array of claim 8 , wherein the first input is a negative input of the negative feedback operational amplifier, and the second input is a positive input of the negative feedback operational amplifier.

10. The memristive cross-bar array of claim 1 , wherein the circuits comprise differential amplifiers, wherein each respective differential amplifier of the differential amplifiers has a first input connected to a respective row line of the row lines, and a second input connected to the reference voltage.

11. A method of obtaining a dot product, comprising:
applying first voltage signals to corresponding row lines within a memristive cross-bar array to change resistive values of corresponding memristors located at junctions between the row lines and column lines, the first voltage signals defining matrix values within a matrix of the memristors;
applying second voltage signals to the row lines within the memristive cross-bar array, the second voltage signals defining corresponding vector values;
collecting output currents from the column lines, the collected output currents defining the dot product; and
shifting an operation region of the memristive cross-bar array using differential amplifiers connected to the row lines, based on application of a reference voltage to the differential amplifiers.

12. The method of claim 11 , further comprising applying an initial voltage to each memristor to set the memristors to an initial resistance.

13. The method of claim 11 , wherein the differential amplifiers are negative feedback operational amplifiers.

14. The method of claim 11 , wherein the shifting of the operation region is based on a ratio of a voltage value of an input voltage into the differential amplifiers and the reference voltage.

15. The method of claim 14 , wherein the ratio comprises voltages such that the reference voltage is equal to a maximum voltage of the input voltage divided by two.

16. The method of claim 11 , wherein each respective differential amplifier of the differential amplifiers has a first input connected to a respective row line of the row lines, and a second input connected to the reference voltage.

17. A computing device comprising:
a processor; and
a memristor cross-bar array coupled to the processor, the memristor cross-bar array comprising:
a plurality of row lines;
a plurality of column lines intersecting the row lines to form respective junctions;
a plurality of memristor devices coupled between the row lines and the column lines at the junctions,
the row lines to provide programming signals at the memristor devices, the programming signals defining matrix values within a matrix of the memristor devices; and
the row lines to provide vector signals at the memristor devices, the vector signals defining vector values to be applied to the memristor devices; and

a plurality of circuits connected to the row lines to apply a reference voltage to each memristor device to set the memristor devices to an initial resistance,

wherein the circuits are to shift an operation region of the memristive cross-bar array based on a ratio of a voltage of a voltage input into the circuits and the reference voltage.

18. The computing device of claim 17 , wherein the memristor cross-bar array further comprises a current collection line to collect all currents output from the memristor devices through the respective column lines, the collected current equaling a dot product of the matrix values and the vector values.

19. The computing device of claim 17 , wherein the processor is to input an output of the memristor cross-bar array to a computer program.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Ge Ning
• Yang Jianhua
• Strachan John Paul
• Hu Miao

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G06F17/11

  for solving equations {, e.g. nonlinear equations, general mathematical optimization problems (optimization specially adapted for a specific administrative, business or logistic context G06Q10/04)} · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C2213/15

  Current-voltage curve · CPC title