Random number generator functions in memory

Patent metadata

Field	Value
Publication number	US-9323499-B2
Application number	US-201213725788-A
Country	US
Kind code	B2
Filing date	Dec 21, 2012
Priority date	Nov 15, 2012
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A memory device includes but is not limited to a substrate, a non-volatile memory array integrated on the substrate, and random number generator logic integrated with the non-volatile memory array on the substrate. The random number generator logic is operable to perform at least one random number generator function in association with the non-volatile memory array. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure.

First claim

What is claimed is:

1. A memory device comprising:
a substrate;
a non-volatile memory array integrated on the substrate, wherein the non-volatile memory array is partitioned into a plurality of memory blocks; and
random number generator logic integrated with the non-volatile memory array on the substrate, the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array partitioned into a plurality of logic blocks spatially distributed over the non-volatile memory array wherein one or more of the plurality of logic blocks are associated with one or more of the plurality of memory blocks.

2. The memory device according to claim 1 wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to supply a source of entropy for generating random numbers.

3. The memory device according to claim 1 wherein:
the non-volatile memory array includes a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types; and
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to use the plurality of non-volatile memory segments characterized by the respective plurality of non-volatile memory types to supply a source of entropy for generating random numbers.

4. The memory device according to claim 1 further comprising:
at least one sensor operable to detect at least one operating condition, wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to use the at least one operating condition to supply a source of entropy for generating random numbers.

5. The memory device according to claim 1 further comprising:
at least one sensor operable to detect at least one operating condition, wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to monitor the at least one operating condition, monitor memory accesses, analyze the monitored at least one operating condition and memory accesses, and determine a source of entropy for generating random numbers based on the analysis of the monitored at least one operating condition and memory accesses.

6. The memory device according to claim 1 wherein:
the non-volatile memory array includes at least in part lossy memory; and
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable use the lossy memory to supply a source of entropy for generating random numbers.

7. The memory device according to claim 1 wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to access a time signal and determine a source of entropy for generating random numbers based on the time signal.

8. The memory device according to claim 1 wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to access a time signal, monitor memory accesses referenced by the time signal, and determine a source of entropy for generating random numbers based on the time signal and the memory accesses referenced by the time signal.

9. The memory device according to claim 1 wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to monitor phenomena detectable at the memory device and determine a source of entropy for generating random numbers based on the monitored phenomena.

10. The memory device according to claim 1 wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to accumulate and communicate information about phenomena associated with use of the memory device and determine a source of entropy for generating random numbers based on the monitored phenomena.

11. The memory device according to claim 1 wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to accumulate and communicate information about phenomena associated with at least one entity in association with the memory device and determine a source of entropy for generating random numbers based on the monitored phenomena.

12. The memory device according to claim 1 wherein:
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to supply a seed for a pseudo-random number generator in association with the non-volatile memory array.

13. The memory device according to claim 1 wherein:
the non-volatile memory array includes a plurality of non-volatile memory segments characterized by a respective plurality of non-volatile memory types; and
the random number generator logic operable to perform at least one random number generator function in association with the non-volatile memory array is operable to supply a seed for a pseudo-random number generator in association with the plurality of non-volatile memory segments characterized by the respective plurality of non-volatile memory types.

14. The memory device according to claim 1 further comprising:
encryption logic integrated with the non-volatile memory array on the substrate, the encryption logic operable to perform at least one encryption/decryption function associated with the non-volatile memory array.

15. The memory device according to claim 1 further comprising:
encryption logic integrated with the non-volatile memory array on the substrate, the encryption logic operable to perform at least one encryption/decryption function associated with the non-volatile memory array that increases throughput of encryption-type operations in combination with a device external to the memory device.

16. The memory device according to claim 1 further comprising:
encryption logic integrated with the non-volatile memory array on the substrate, the encryption logic operable to perform at least one encryption/decryption function associated with the non-volatile memory array that secures at least one encryption key from access by a device external to the memory device.

17. The memory device according to claim 1 further comprising:
hash logic integrated with the non-volatile memory array on the substrate, the hash logic operable to perform a hash function using randomness supplied by the random number generator logic.

18. The memory device according to claim 1 further comprising:
searching logic integrated with the non-volatile memory array on the substrate, the searching logic operable to perform amortized searching using randomness supplied by the random number generator logic.

19. The memory device according to claim 1 further comprising:
sorting logic integrated with the non-volatile memory array on the substrate, the sorting logic operable to perform data sorting usi

Assignees

• Elwha Llc A Ltd Liability Corp State Delaware
• Elwha Llc

Inventors

• Hyde Roderick A
• Pasch Nicholas F
• Tegreene Clarence T

Classifications

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title